1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2005 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// Alpha ISA description file.
34//
35////////////////////////////////////////////////////////////////////
36
37
38////////////////////////////////////////////////////////////////////
39//
40// Output include file directives.
41//
42
43output header {{
44#include <iomanip>
45#include <iostream>
46#include <sstream>
47
48#include "arch/alpha/faults.hh"
49#include "arch/alpha/types.hh"
50#include "config/ss_compatible_fp.hh"
51#include "cpu/static_inst.hh"
52#include "mem/packet.hh"
53#include "mem/request.hh" // some constructors use MemReq flags
54}};
55
56output decoder {{
57#include <cmath>
58
59#include "arch/alpha/registers.hh"
60#include "arch/alpha/regredir.hh"
61#include "base/loader/symtab.hh"
62#include "base/cprintf.hh"
63#include "base/fenv.hh"
64#include "config/ss_compatible_fp.hh"
65#include "cpu/thread_context.hh" // for Jump::branchTarget()
66#include "mem/packet.hh"
67
68using namespace AlphaISA;
69}};
70
71output exec {{
72#include <math.h>
73
74#include "arch/alpha/registers.hh"
75#include "arch/alpha/regredir.hh"
76#include "arch/generic/memhelpers.hh"
77#include "base/cp_annotate.hh"
78#include "base/fenv.hh"
79#include "config/ss_compatible_fp.hh"
80#include "cpu/base.hh"
81#include "cpu/exetrace.hh"
82#include "mem/packet.hh"
83#include "mem/packet_access.hh"
84#include "sim/pseudo_inst.hh"
85#include "sim/sim_exit.hh"
86
87using namespace AlphaISA;
88}};
89
90////////////////////////////////////////////////////////////////////
91//
92// Namespace statement. Everything below this line will be in the
93// AlphaISAInst namespace.
94//
95
96
97namespace AlphaISA;
98
99////////////////////////////////////////////////////////////////////
100//
101// Bitfield definitions.
102//
103
104// Universal (format-independent) fields
105def bitfield PALMODE <32:32>;
106def bitfield OPCODE <31:26>;
107def bitfield RA <25:21>;
108def bitfield RB <20:16>;
109
110// Memory format
111def signed bitfield MEMDISP <15: 0>; // displacement
112def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
113
114// Memory-format jumps
115def bitfield JMPFUNC <15:14>; // function code (disp<15:14>)
116def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>)
117
118// Branch format
119def signed bitfield BRDISP <20: 0>; // displacement
120
121// Integer operate format(s>;
122def bitfield INTIMM <20:13>; // integer immediate (literal)
123def bitfield IMM <12:12>; // immediate flag
124def bitfield INTFUNC <11: 5>; // function code
125def bitfield RC < 4: 0>; // dest reg
126
127// Floating-point operate format
128def bitfield FA <25:21>;
129def bitfield FB <20:16>;
130def bitfield FP_FULLFUNC <15: 5>; // complete function code
131 def bitfield FP_TRAPMODE <15:13>; // trapping mode
132 def bitfield FP_ROUNDMODE <12:11>; // rounding mode
133 def bitfield FP_TYPEFUNC <10: 5>; // type+func: handiest for decoding
134 def bitfield FP_SRCTYPE <10: 9>; // source reg type
135 def bitfield FP_SHORTFUNC < 8: 5>; // short function code
136 def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
137def bitfield FC < 4: 0>; // dest reg
138
139// PALcode format
140def bitfield PALFUNC <25: 0>; // function code
141
142// EV5 PAL instructions:
143// HW_LD/HW_ST
144def bitfield HW_LDST_PHYS <15>; // address is physical
145def bitfield HW_LDST_ALT <14>; // use ALT_MODE IPR
146def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
147def bitfield HW_LDST_QUAD <12>; // size: 0=32b, 1=64b
148def bitfield HW_LDST_VPTE <11>; // HW_LD only: is PTE fetch
149def bitfield HW_LDST_LOCK <10>; // HW_LD only: is load locked
150def bitfield HW_LDST_COND <10>; // HW_ST only: is store conditional
151def signed bitfield HW_LDST_DISP <9:0>; // signed displacement
152
153// HW_REI
154def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
155def bitfield HW_REI_MBZ <13: 0>; // must be zero
156
157// HW_MTPR/MW_MFPR
158def bitfield HW_IPR_IDX <15:0>; // IPR index
159
160// M5 instructions
161def bitfield M5FUNC <7:0>;
162
163def operand_types {{
164 'sb' : 'int8_t',
165 'ub' : 'uint8_t',
166 'sw' : 'int16_t',
167 'uw' : 'uint16_t',
168 'sl' : 'int32_t',
169 'ul' : 'uint32_t',
170 'sq' : 'int64_t',
171 'uq' : 'uint64_t',
172 'sf' : 'float',
173 'df' : 'double'
174}};
175
176def operands {{
177 # Int regs default to unsigned, but code should not count on this.
178 # For clarity, descriptions that depend on unsigned behavior should
179 # explicitly specify '_uq'.
180 'Ra': ('IntReg', 'uq', 'PALMODE ? reg_redir[RA] : RA',
181 'IsInteger', 1),
182 'Rb': ('IntReg', 'uq', 'PALMODE ? reg_redir[RB] : RB',
183 'IsInteger', 2),
184 'Rc': ('IntReg', 'uq', 'PALMODE ? reg_redir[RC] : RC',
185 'IsInteger', 3),
186 'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
187 'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
188 'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
189 'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
190 'PC': ('PCState', 'uq', 'pc', ( None, None, 'IsControl' ), 4),
191 'NPC': ('PCState', 'uq', 'npc', ( None, None, 'IsControl' ), 4),
192 'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1),
193 'FPCR': ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1),
194 'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1),
195 # The next two are hacks for non-full-system call-pal emulation
196 'R0': ('IntReg', 'uq', '0', None, 1),
197 'R16': ('IntReg', 'uq', '16', None, 1),
198 'R17': ('IntReg', 'uq', '17', None, 1),
199 'R18': ('IntReg', 'uq', '18', None, 1)
200}};
201
202////////////////////////////////////////////////////////////////////
203//
204// Basic instruction classes/templates/formats etc.
205//
206
207output header {{
208// uncomment the following to get SimpleScalar-compatible disassembly
209// (useful for diffing output traces).
210// #define SS_COMPATIBLE_DISASSEMBLY
211
212 /**
213 * Base class for all Alpha static instructions.
214 */
215 class AlphaStaticInst : public StaticInst
216 {
217 protected:
218
219 /// Make AlphaISA register dependence tags directly visible in
220 /// this class and derived classes. Maybe these should really
221 /// live here and not in the AlphaISA namespace.
222 enum DependenceTags {
223 FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
224 };
225
226 /// Constructor.
227 AlphaStaticInst(const char *mnem, ExtMachInst _machInst,
228 OpClass __opClass)
229 : StaticInst(mnem, _machInst, __opClass)
230 {
231 }
232
233 /// Print a register name for disassembly given the unique
234 /// dependence tag number (FP or int).
235 void printReg(std::ostream &os, int reg) const;
236
237 std::string
238 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
239
240 void
241 advancePC(AlphaISA::PCState &pcState) const
242 {
243 pcState.advance();
244 }
245 };
246}};
247
248output decoder {{
249 void
250 AlphaStaticInst::printReg(std::ostream &os, int reg) const
251 {
252 if (reg < FP_Base_DepTag) {
253 ccprintf(os, "r%d", reg);
254 }
255 else {
256 ccprintf(os, "f%d", reg - FP_Base_DepTag);
257 }
258 }
259
260 std::string
261 AlphaStaticInst::generateDisassembly(Addr pc,
262 const SymbolTable *symtab) const
263 {
264 std::stringstream ss;
265
266 ccprintf(ss, "%-10s ", mnemonic);
267
268 // just print the first two source regs... if there's
269 // a third one, it's a read-modify-write dest (Rc),
270 // e.g. for CMOVxx
271 if (_numSrcRegs > 0) {
272 printReg(ss, _srcRegIdx[0]);
273 }
274 if (_numSrcRegs > 1) {
275 ss << ",";
276 printReg(ss, _srcRegIdx[1]);
277 }
278
279 // just print the first dest... if there's a second one,
280 // it's generally implicit
281 if (_numDestRegs > 0) {
282 if (_numSrcRegs > 0)
283 ss << ",";
284 printReg(ss, _destRegIdx[0]);
285 }
286
287 return ss.str();
288 }
289}};
290
291// Declarations for execute() methods.
292def template BasicExecDeclare {{
293 Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
294}};
295
296// Basic instruction class declaration template.
297def template BasicDeclare {{
298 /**
299 * Static instruction class for "%(mnemonic)s".
300 */
301 class %(class_name)s : public %(base_class)s
302 {
303 public:
304 /// Constructor.
305 %(class_name)s(ExtMachInst machInst);
306
307 %(BasicExecDeclare)s
308 };
309}};
310
311// Basic instruction class constructor template.
312def template BasicConstructor {{
313 inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
314 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
315 {
316 %(constructor)s;
317 }
318}};
319
320// Basic instruction class execute method template.
321def template BasicExecute {{
322 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
323 Trace::InstRecord *traceData) const
324 {
325 Fault fault = NoFault;
326
327 %(fp_enable_check)s;
328 %(op_decl)s;
329 %(op_rd)s;
330 %(code)s;
331
332 if (fault == NoFault) {
333 %(op_wb)s;
334 }
335
336 return fault;
337 }
338}};
339
340// Basic decode template.
341def template BasicDecode {{
342 return new %(class_name)s(machInst);
343}};
344
345// Basic decode template, passing mnemonic in as string arg to constructor.
346def template BasicDecodeWithMnemonic {{
347 return new %(class_name)s("%(mnemonic)s", machInst);
348}};
349
350// The most basic instruction format... used only for a few misc. insts
351def format BasicOperate(code, *flags) {{
352 iop = InstObjParams(name, Name, 'AlphaStaticInst', code, flags)
353 header_output = BasicDeclare.subst(iop)
354 decoder_output = BasicConstructor.subst(iop)
355 decode_block = BasicDecode.subst(iop)
356 exec_output = BasicExecute.subst(iop)
357}};
358
359
360
361////////////////////////////////////////////////////////////////////
362//
363// Nop
364//
365
366output header {{
367 /**
368 * Static instruction class for no-ops. This is a leaf class.
369 */
370 class Nop : public AlphaStaticInst
371 {
372 /// Disassembly of original instruction.
373 const std::string originalDisassembly;
374
375 public:
376 /// Constructor
377 Nop(const std::string _originalDisassembly, ExtMachInst _machInst)
378 : AlphaStaticInst("nop", _machInst, No_OpClass),
379 originalDisassembly(_originalDisassembly)
380 {
381 flags[IsNop] = true;
382 }
383
384 ~Nop() { }
385
386 std::string
387 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
388
389 %(BasicExecDeclare)s
390 };
391
392 /// Helper function for decoding nops. Substitute Nop object
393 /// for original inst passed in as arg (and delete latter).
394 static inline
395 AlphaStaticInst *
396 makeNop(AlphaStaticInst *inst)
397 {
398 AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
399 delete inst;
400 return nop;
401 }
402}};
403
404output decoder {{
405 std::string Nop::generateDisassembly(Addr pc,
406 const SymbolTable *symtab) const
407 {
408#ifdef SS_COMPATIBLE_DISASSEMBLY
409 return originalDisassembly;
410#else
411 return csprintf("%-10s (%s)", "nop", originalDisassembly);
412#endif
413 }
414}};
415
416output exec {{
417 Fault
418 Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
419 {
420 return NoFault;
421 }
422}};
423
424// integer & FP operate instructions use Rc as dest, so check for
425// Rc == 31 to detect nops
426def template OperateNopCheckDecode {{
427 {
428 AlphaStaticInst *i = new %(class_name)s(machInst);
429 if (RC == 31) {
430 i = makeNop(i);
431 }
432 return i;
433 }
434}};
435
436// Like BasicOperate format, but generates NOP if RC/FC == 31
437def format BasicOperateWithNopCheck(code, *opt_args) {{
438 iop = InstObjParams(name, Name, 'AlphaStaticInst', code, opt_args)
439 header_output = BasicDeclare.subst(iop)
440 decoder_output = BasicConstructor.subst(iop)
441 decode_block = OperateNopCheckDecode.subst(iop)
442 exec_output = BasicExecute.subst(iop)
443}};
444
445// Integer instruction templates, formats, etc.
446##include "int.isa"
447
448// Floating-point instruction templates, formats, etc.
449##include "fp.isa"
450
451// Memory instruction templates, formats, etc.
452##include "mem.isa"
453
454// Branch/jump instruction templates, formats, etc.
455##include "branch.isa"
456
457// PAL instruction templates, formats, etc.
458##include "pal.isa"
459
460// Opcdec fault instruction templates, formats, etc.
461##include "opcdec.isa"
462
463// Unimplemented instruction templates, formats, etc.
464##include "unimp.isa"
465
466// Unknown instruction templates, formats, etc.
467##include "unknown.isa"
468
469// Execution utility functions
470##include "util.isa"
471
472// The actual decoder
473##include "decoder.isa"