1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2005 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// Alpha ISA description file.
34//
35////////////////////////////////////////////////////////////////////
36
37
38////////////////////////////////////////////////////////////////////
39//
40// Output include file directives.
41//
42
43output header {{
44#include <sstream>
45#include <iostream>
46#include <iomanip>
47
48#include "config/ss_compatible_fp.hh"
49#include "cpu/static_inst.hh"
50#include "arch/alpha/faults.hh"
51#include "mem/request.hh" // some constructors use MemReq flags
52}};
53
54output decoder {{
55#include "base/cprintf.hh"
56#include "base/fenv.hh"
57#include "base/loader/symtab.hh"
58#include "config/ss_compatible_fp.hh"
59#include "cpu/thread_context.hh" // for Jump::branchTarget()
60
61#include <math.h>
62
63using namespace AlphaISA;
64}};
65
66output exec {{
67#include <math.h>
68
69#if FULL_SYSTEM
70#include "sim/pseudo_inst.hh"
71#endif
72#include "base/fenv.hh"
73#include "config/ss_compatible_fp.hh"
74#include "cpu/base.hh"
75#include "cpu/exetrace.hh"
76#include "sim/sim_exit.hh"
77#include "mem/packet_impl.hh"
78
79using namespace AlphaISA;
80}};
81
82////////////////////////////////////////////////////////////////////
83//
84// Namespace statement. Everything below this line will be in the
85// AlphaISAInst namespace.
86//
87
88
89namespace AlphaISA;
90
91////////////////////////////////////////////////////////////////////
92//
93// Bitfield definitions.
94//
95
96// Universal (format-independent) fields
97def bitfield PALMODE <32:32>;
98def bitfield OPCODE <31:26>;
99def bitfield RA <25:21>;
100def bitfield RB <20:16>;
101
102// Memory format
103def signed bitfield MEMDISP <15: 0>; // displacement
104def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
105
106// Memory-format jumps
107def bitfield JMPFUNC <15:14>; // function code (disp<15:14>)
108def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>)
109
110// Branch format
111def signed bitfield BRDISP <20: 0>; // displacement
112
113// Integer operate format(s>;
114def bitfield INTIMM <20:13>; // integer immediate (literal)
115def bitfield IMM <12:12>; // immediate flag
116def bitfield INTFUNC <11: 5>; // function code
117def bitfield RC < 4: 0>; // dest reg
118
119// Floating-point operate format
120def bitfield FA <25:21>;
121def bitfield FB <20:16>;
122def bitfield FP_FULLFUNC <15: 5>; // complete function code
123 def bitfield FP_TRAPMODE <15:13>; // trapping mode
124 def bitfield FP_ROUNDMODE <12:11>; // rounding mode
125 def bitfield FP_TYPEFUNC <10: 5>; // type+func: handiest for decoding
126 def bitfield FP_SRCTYPE <10: 9>; // source reg type
127 def bitfield FP_SHORTFUNC < 8: 5>; // short function code
128 def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
129def bitfield FC < 4: 0>; // dest reg
130
131// PALcode format
132def bitfield PALFUNC <25: 0>; // function code
133
134// EV5 PAL instructions:
135// HW_LD/HW_ST
136def bitfield HW_LDST_PHYS <15>; // address is physical
137def bitfield HW_LDST_ALT <14>; // use ALT_MODE IPR
138def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
139def bitfield HW_LDST_QUAD <12>; // size: 0=32b, 1=64b
140def bitfield HW_LDST_VPTE <11>; // HW_LD only: is PTE fetch
141def bitfield HW_LDST_LOCK <10>; // HW_LD only: is load locked
142def bitfield HW_LDST_COND <10>; // HW_ST only: is store conditional
143def signed bitfield HW_LDST_DISP <9:0>; // signed displacement
144
145// HW_REI
146def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
147def bitfield HW_REI_MBZ <13: 0>; // must be zero
148
149// HW_MTPR/MW_MFPR
150def bitfield HW_IPR_IDX <15:0>; // IPR index
151
152// M5 instructions
153def bitfield M5FUNC <7:0>;
154
155def operand_types {{
156 'sb' : ('signed int', 8),
157 'ub' : ('unsigned int', 8),
158 'sw' : ('signed int', 16),
159 'uw' : ('unsigned int', 16),
160 'sl' : ('signed int', 32),
161 'ul' : ('unsigned int', 32),
162 'sq' : ('signed int', 64),
163 'uq' : ('unsigned int', 64),
164 'sf' : ('float', 32),
165 'df' : ('float', 64)
166}};
167
168def operands {{
169 # Int regs default to unsigned, but code should not count on this.
170 # For clarity, descriptions that depend on unsigned behavior should
171 # explicitly specify '.uq'.
172 'Ra': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RA] : RA',
173 'IsInteger', 1),
174 'Rb': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RB] : RB',
175 'IsInteger', 2),
176 'Rc': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RC] : RC',
177 'IsInteger', 3),
178 'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
179 'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
180 'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
181 'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
182 'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
183 'Runiq': ('ControlReg', 'uq', 'TheISA::Uniq_DepTag', None, 1),
184 'FPCR': (' ControlReg', 'uq', 'TheISA::Fpcr_DepTag', None, 1),
185 # The next two are hacks for non-full-system call-pal emulation
186 'R0': ('IntReg', 'uq', '0', None, 1),
187 'R16': ('IntReg', 'uq', '16', None, 1),
188 'R17': ('IntReg', 'uq', '17', None, 1),
189 'R18': ('IntReg', 'uq', '18', None, 1)
190}};
191
192////////////////////////////////////////////////////////////////////
193//
194// Basic instruction classes/templates/formats etc.
195//
196
197output header {{
198// uncomment the following to get SimpleScalar-compatible disassembly
199// (useful for diffing output traces).
200// #define SS_COMPATIBLE_DISASSEMBLY
201
202 /**
203 * Base class for all Alpha static instructions.
204 */
205 class AlphaStaticInst : public StaticInst
206 {
207 protected:
208
209 /// Make AlphaISA register dependence tags directly visible in
210 /// this class and derived classes. Maybe these should really
211 /// live here and not in the AlphaISA namespace.
212 enum DependenceTags {
213 FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
214 Fpcr_DepTag = AlphaISA::Fpcr_DepTag,
215 Uniq_DepTag = AlphaISA::Uniq_DepTag,
216 Lock_Flag_DepTag = AlphaISA::Lock_Flag_DepTag,
217 Lock_Addr_DepTag = AlphaISA::Lock_Addr_DepTag,
218 IPR_Base_DepTag = AlphaISA::IPR_Base_DepTag
219 };
220
221 /// Constructor.
222 AlphaStaticInst(const char *mnem, ExtMachInst _machInst,
223 OpClass __opClass)
224 : StaticInst(mnem, _machInst, __opClass)
225 {
226 }
227
228 /// Print a register name for disassembly given the unique
229 /// dependence tag number (FP or int).
230 void printReg(std::ostream &os, int reg) const;
231
232 std::string
233 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
234 };
235}};
236
237output decoder {{
238 void
239 AlphaStaticInst::printReg(std::ostream &os, int reg) const
240 {
241 if (reg < FP_Base_DepTag) {
242 ccprintf(os, "r%d", reg);
243 }
244 else {
245 ccprintf(os, "f%d", reg - FP_Base_DepTag);
246 }
247 }
248
249 std::string
250 AlphaStaticInst::generateDisassembly(Addr pc,
251 const SymbolTable *symtab) const
252 {
253 std::stringstream ss;
254
255 ccprintf(ss, "%-10s ", mnemonic);
256
257 // just print the first two source regs... if there's
258 // a third one, it's a read-modify-write dest (Rc),
259 // e.g. for CMOVxx
260 if (_numSrcRegs > 0) {
261 printReg(ss, _srcRegIdx[0]);
262 }
263 if (_numSrcRegs > 1) {
264 ss << ",";
265 printReg(ss, _srcRegIdx[1]);
266 }
267
268 // just print the first dest... if there's a second one,
269 // it's generally implicit
270 if (_numDestRegs > 0) {
271 if (_numSrcRegs > 0)
272 ss << ",";
273 printReg(ss, _destRegIdx[0]);
274 }
275
276 return ss.str();
277 }
278}};
279
280// Declarations for execute() methods.
281def template BasicExecDeclare {{
282 Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
283}};
284
285// Basic instruction class declaration template.
286def template BasicDeclare {{
287 /**
288 * Static instruction class for "%(mnemonic)s".
289 */
290 class %(class_name)s : public %(base_class)s
291 {
292 public:
293 /// Constructor.
294 %(class_name)s(ExtMachInst machInst);
295
296 %(BasicExecDeclare)s
297 };
298}};
299
300// Basic instruction class constructor template.
301def template BasicConstructor {{
302 inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
303 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
304 {
305 %(constructor)s;
306 }
307}};
308
309// Basic instruction class execute method template.
310def template BasicExecute {{
311 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
312 Trace::InstRecord *traceData) const
313 {
314 Fault fault = NoFault;
315
316 %(fp_enable_check)s;
317 %(op_decl)s;
318 %(op_rd)s;
319 %(code)s;
320
321 if (fault == NoFault) {
322 %(op_wb)s;
323 }
324
325 return fault;
326 }
327}};
328
329// Basic decode template.
330def template BasicDecode {{
331 return new %(class_name)s(machInst);
332}};
333
334// Basic decode template, passing mnemonic in as string arg to constructor.
335def template BasicDecodeWithMnemonic {{
336 return new %(class_name)s("%(mnemonic)s", machInst);
337}};
338
339// The most basic instruction format... used only for a few misc. insts
340def format BasicOperate(code, *flags) {{
341 iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code), flags)
342 header_output = BasicDeclare.subst(iop)
343 decoder_output = BasicConstructor.subst(iop)
344 decode_block = BasicDecode.subst(iop)
345 exec_output = BasicExecute.subst(iop)
346}};
347
348
349
350////////////////////////////////////////////////////////////////////
351//
352// Nop
353//
354
355output header {{
356 /**
357 * Static instruction class for no-ops. This is a leaf class.
358 */
359 class Nop : public AlphaStaticInst
360 {
361 /// Disassembly of original instruction.
362 const std::string originalDisassembly;
363
364 public:
365 /// Constructor
366 Nop(const std::string _originalDisassembly, ExtMachInst _machInst)
367 : AlphaStaticInst("nop", _machInst, No_OpClass),
368 originalDisassembly(_originalDisassembly)
369 {
370 flags[IsNop] = true;
371 }
372
373 ~Nop() { }
374
375 std::string
376 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
377
378 %(BasicExecDeclare)s
379 };
380
381 /// Helper function for decoding nops. Substitute Nop object
382 /// for original inst passed in as arg (and delete latter).
383 static inline
384 AlphaStaticInst *
385 makeNop(AlphaStaticInst *inst)
386 {
387 AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
388 delete inst;
389 return nop;
390 }
391}};
392
393output decoder {{
394 std::string Nop::generateDisassembly(Addr pc,
395 const SymbolTable *symtab) const
396 {
397#ifdef SS_COMPATIBLE_DISASSEMBLY
398 return originalDisassembly;
399#else
400 return csprintf("%-10s (%s)", "nop", originalDisassembly);
401#endif
402 }
403}};
404
405output exec {{
406 Fault
407 Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
408 {
409 return NoFault;
410 }
411}};
412
413// integer & FP operate instructions use Rc as dest, so check for
414// Rc == 31 to detect nops
415def template OperateNopCheckDecode {{
416 {
417 AlphaStaticInst *i = new %(class_name)s(machInst);
418 if (RC == 31) {
419 i = makeNop(i);
420 }
421 return i;
422 }
423}};
424
425// Like BasicOperate format, but generates NOP if RC/FC == 31
426def format BasicOperateWithNopCheck(code, *opt_args) {{
427 iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code),
428 opt_args)
429 header_output = BasicDeclare.subst(iop)
430 decoder_output = BasicConstructor.subst(iop)
431 decode_block = OperateNopCheckDecode.subst(iop)
432 exec_output = BasicExecute.subst(iop)
433}};
434
435// Integer instruction templates, formats, etc.
436##include "int.isa"
437
438// Floating-point instruction templates, formats, etc.
439##include "fp.isa"
440
441// Memory instruction templates, formats, etc.
442##include "mem.isa"
443
444// Branch/jump instruction templates, formats, etc.
445##include "branch.isa"
446
447// PAL instruction templates, formats, etc.
448##include "pal.isa"
449
450// Opcdec fault instruction templates, formats, etc.
451##include "opcdec.isa"
452
453// Unimplemented instruction templates, formats, etc.
454##include "unimp.isa"
455
456// Unknown instruction templates, formats, etc.
457##include "unknown.isa"
458
459// Execution utility functions
460##include "util.isa"
461
462// The actual decoder
463##include "decoder.isa"