1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2005 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28
29output header {{
30#include <sstream>
31#include <iostream>
32#include <iomanip>
33
34#include "config/ss_compatible_fp.hh"
35#include "cpu/static_inst.hh"
36#include "arch/alpha/faults.hh"
37#include "mem/request.hh" // some constructors use MemReq flags
38}};
39
40output decoder {{
41#include "base/cprintf.hh"
42#include "base/fenv.hh"
43#include "base/loader/symtab.hh"
44#include "config/ss_compatible_fp.hh"
45#include "cpu/exec_context.hh" // for Jump::branchTarget()
46
47#include <math.h>
48
49using namespace AlphaISA;
50}};
51
52output exec {{
53#include <math.h>
54
55#if FULL_SYSTEM
56#include "sim/pseudo_inst.hh"
57#endif
58#include "base/fenv.hh"
59#include "config/ss_compatible_fp.hh"
60#include "cpu/base.hh"
61#include "cpu/exetrace.hh"
62#include "sim/sim_exit.hh"
63#include "mem/packet_impl.hh"
64
65using namespace AlphaISA;
66}};
67
68////////////////////////////////////////////////////////////////////
69//
70// Namespace statement. Everything below this line will be in the
71// AlphaISAInst namespace.
72//
73
74
75namespace AlphaISA;
76
77////////////////////////////////////////////////////////////////////
78//
79// Bitfield definitions.
80//
81
82// Universal (format-independent) fields
83def bitfield PALMODE <32:32>;
84def bitfield OPCODE <31:26>;
85def bitfield RA <25:21>;
86def bitfield RB <20:16>;
87
88// Memory format
89def signed bitfield MEMDISP <15: 0>; // displacement
90def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
91
92// Memory-format jumps
93def bitfield JMPFUNC <15:14>; // function code (disp<15:14>)
94def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>)
95
96// Branch format
97def signed bitfield BRDISP <20: 0>; // displacement
98
99// Integer operate format(s>;
100def bitfield INTIMM <20:13>; // integer immediate (literal)
101def bitfield IMM <12:12>; // immediate flag
102def bitfield INTFUNC <11: 5>; // function code
103def bitfield RC < 4: 0>; // dest reg
104
105// Floating-point operate format
106def bitfield FA <25:21>;
107def bitfield FB <20:16>;
108def bitfield FP_FULLFUNC <15: 5>; // complete function code
109 def bitfield FP_TRAPMODE <15:13>; // trapping mode
110 def bitfield FP_ROUNDMODE <12:11>; // rounding mode
111 def bitfield FP_TYPEFUNC <10: 5>; // type+func: handiest for decoding
112 def bitfield FP_SRCTYPE <10: 9>; // source reg type
113 def bitfield FP_SHORTFUNC < 8: 5>; // short function code
114 def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
115def bitfield FC < 4: 0>; // dest reg
116
117// PALcode format
118def bitfield PALFUNC <25: 0>; // function code
119
120// EV5 PAL instructions:
121// HW_LD/HW_ST
122def bitfield HW_LDST_PHYS <15>; // address is physical
123def bitfield HW_LDST_ALT <14>; // use ALT_MODE IPR
124def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
125def bitfield HW_LDST_QUAD <12>; // size: 0=32b, 1=64b
126def bitfield HW_LDST_VPTE <11>; // HW_LD only: is PTE fetch
127def bitfield HW_LDST_LOCK <10>; // HW_LD only: is load locked
128def bitfield HW_LDST_COND <10>; // HW_ST only: is store conditional
129def signed bitfield HW_LDST_DISP <9:0>; // signed displacement
130
131// HW_REI
132def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
133def bitfield HW_REI_MBZ <13: 0>; // must be zero
134
135// HW_MTPR/MW_MFPR
136def bitfield HW_IPR_IDX <15:0>; // IPR index
137
138// M5 instructions
139def bitfield M5FUNC <7:0>;
140
141def operand_types {{
142 'sb' : ('signed int', 8),
143 'ub' : ('unsigned int', 8),
144 'sw' : ('signed int', 16),
145 'uw' : ('unsigned int', 16),
146 'sl' : ('signed int', 32),
147 'ul' : ('unsigned int', 32),
148 'sq' : ('signed int', 64),
149 'uq' : ('unsigned int', 64),
150 'sf' : ('float', 32),
151 'df' : ('float', 64)
152}};
153
154def operands {{
155 # Int regs default to unsigned, but code should not count on this.
156 # For clarity, descriptions that depend on unsigned behavior should
157 # explicitly specify '.uq'.
158 'Ra': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RA] : RA',
159 'IsInteger', 1),
160 'Rb': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RB] : RB',
161 'IsInteger', 2),
162 'Rc': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RC] : RC',
163 'IsInteger', 3),
164 'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
165 'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
166 'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
167 'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
168 'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
169 'Runiq': ('ControlReg', 'uq', 'TheISA::Uniq_DepTag', None, 1),
170 'FPCR': (' ControlReg', 'uq', 'TheISA::Fpcr_DepTag', None, 1),
171 # The next two are hacks for non-full-system call-pal emulation
172 'R0': ('IntReg', 'uq', '0', None, 1),
173 'R16': ('IntReg', 'uq', '16', None, 1),
174 'R17': ('IntReg', 'uq', '17', None, 1),
175 'R18': ('IntReg', 'uq', '18', None, 1)
176}};
177
178////////////////////////////////////////////////////////////////////
179//
180// Basic instruction classes/templates/formats etc.
181//
182
183output header {{
184// uncomment the following to get SimpleScalar-compatible disassembly
185// (useful for diffing output traces).
186// #define SS_COMPATIBLE_DISASSEMBLY
187
188 /**
189 * Base class for all Alpha static instructions.
190 */
191 class AlphaStaticInst : public StaticInst
192 {
193 protected:
194
195 /// Make AlphaISA register dependence tags directly visible in
196 /// this class and derived classes. Maybe these should really
197 /// live here and not in the AlphaISA namespace.
198 enum DependenceTags {
199 FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
200 Fpcr_DepTag = AlphaISA::Fpcr_DepTag,
201 Uniq_DepTag = AlphaISA::Uniq_DepTag,
202 Lock_Flag_DepTag = AlphaISA::Lock_Flag_DepTag,
203 Lock_Addr_DepTag = AlphaISA::Lock_Addr_DepTag,
204 IPR_Base_DepTag = AlphaISA::IPR_Base_DepTag
205 };
206
207 /// Constructor.
208 AlphaStaticInst(const char *mnem, ExtMachInst _machInst,
209 OpClass __opClass)
210 : StaticInst(mnem, _machInst, __opClass)
211 {
212 }
213
214 /// Print a register name for disassembly given the unique
215 /// dependence tag number (FP or int).
216 void printReg(std::ostream &os, int reg) const;
217
218 std::string
219 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
220 };
221}};
222
223output decoder {{
224 void
225 AlphaStaticInst::printReg(std::ostream &os, int reg) const
226 {
227 if (reg < FP_Base_DepTag) {
228 ccprintf(os, "r%d", reg);
229 }
230 else {
231 ccprintf(os, "f%d", reg - FP_Base_DepTag);
232 }
233 }
234
235 std::string
236 AlphaStaticInst::generateDisassembly(Addr pc,
237 const SymbolTable *symtab) const
238 {
239 std::stringstream ss;
240
241 ccprintf(ss, "%-10s ", mnemonic);
242
243 // just print the first two source regs... if there's
244 // a third one, it's a read-modify-write dest (Rc),
245 // e.g. for CMOVxx
246 if (_numSrcRegs > 0) {
247 printReg(ss, _srcRegIdx[0]);
248 }
249 if (_numSrcRegs > 1) {
250 ss << ",";
251 printReg(ss, _srcRegIdx[1]);
252 }
253
254 // just print the first dest... if there's a second one,
255 // it's generally implicit
256 if (_numDestRegs > 0) {
257 if (_numSrcRegs > 0)
258 ss << ",";
259 printReg(ss, _destRegIdx[0]);
260 }
261
262 return ss.str();
263 }
264}};
265
266// Declarations for execute() methods.
267def template BasicExecDeclare {{
268 Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
269}};
270
271// Basic instruction class declaration template.
272def template BasicDeclare {{
273 /**
274 * Static instruction class for "%(mnemonic)s".
275 */
276 class %(class_name)s : public %(base_class)s
277 {
278 public:
279 /// Constructor.
280 %(class_name)s(ExtMachInst machInst);
281
282 %(BasicExecDeclare)s
283 };
284}};
285
286// Basic instruction class constructor template.
287def template BasicConstructor {{
288 inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
289 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
290 {
291 %(constructor)s;
292 }
293}};
294
295// Basic instruction class execute method template.
296def template BasicExecute {{
297 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
298 Trace::InstRecord *traceData) const
299 {
300 Fault fault = NoFault;
301
302 %(fp_enable_check)s;
303 %(op_decl)s;
304 %(op_rd)s;
305 %(code)s;
306
307 if (fault == NoFault) {
308 %(op_wb)s;
309 }
310
311 return fault;
312 }
313}};
314
315// Basic decode template.
316def template BasicDecode {{
317 return new %(class_name)s(machInst);
318}};
319
320// Basic decode template, passing mnemonic in as string arg to constructor.
321def template BasicDecodeWithMnemonic {{
322 return new %(class_name)s("%(mnemonic)s", machInst);
323}};
324
325// The most basic instruction format... used only for a few misc. insts
326def format BasicOperate(code, *flags) {{
327 iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code), flags)
328 header_output = BasicDeclare.subst(iop)
329 decoder_output = BasicConstructor.subst(iop)
330 decode_block = BasicDecode.subst(iop)
331 exec_output = BasicExecute.subst(iop)
332}};
333
334
335
336////////////////////////////////////////////////////////////////////
337//
338// Nop
339//
340
341output header {{
342 /**
343 * Static instruction class for no-ops. This is a leaf class.
344 */
345 class Nop : public AlphaStaticInst
346 {
347 /// Disassembly of original instruction.
348 const std::string originalDisassembly;
349
350 public:
351 /// Constructor
352 Nop(const std::string _originalDisassembly, ExtMachInst _machInst)
353 : AlphaStaticInst("nop", _machInst, No_OpClass),
354 originalDisassembly(_originalDisassembly)
355 {
356 flags[IsNop] = true;
357 }
358
359 ~Nop() { }
360
361 std::string
362 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
363
364 %(BasicExecDeclare)s
365 };
366
367 /// Helper function for decoding nops. Substitute Nop object
368 /// for original inst passed in as arg (and delete latter).
369 static inline
370 AlphaStaticInst *
371 makeNop(AlphaStaticInst *inst)
372 {
373 AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
374 delete inst;
375 return nop;
376 }
377}};
378
379output decoder {{
380 std::string Nop::generateDisassembly(Addr pc,
381 const SymbolTable *symtab) const
382 {
383#ifdef SS_COMPATIBLE_DISASSEMBLY
384 return originalDisassembly;
385#else
386 return csprintf("%-10s (%s)", "nop", originalDisassembly);
387#endif
388 }
389}};
390
391output exec {{
392 Fault
393 Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
394 {
395 return NoFault;
396 }
397}};
398
399// integer & FP operate instructions use Rc as dest, so check for
400// Rc == 31 to detect nops
401def template OperateNopCheckDecode {{
402 {
403 AlphaStaticInst *i = new %(class_name)s(machInst);
404 if (RC == 31) {
405 i = makeNop(i);
406 }
407 return i;
408 }
409}};
410
411// Like BasicOperate format, but generates NOP if RC/FC == 31
412def format BasicOperateWithNopCheck(code, *opt_args) {{
413 iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code),
414 opt_args)
415 header_output = BasicDeclare.subst(iop)
416 decoder_output = BasicConstructor.subst(iop)
417 decode_block = OperateNopCheckDecode.subst(iop)
418 exec_output = BasicExecute.subst(iop)
419}};
420
421// Integer instruction templates, formats, etc.
422##include "int.isa"
423
424// Floating-point instruction templates, formats, etc.
425##include "fp.isa"
426
427// Memory instruction templates, formats, etc.
428##include "mem.isa"
429
430// Branch/jump instruction templates, formats, etc.
431##include "branch.isa"
432
433// PAL instruction templates, formats, etc.
434##include "pal.isa"
435
436// Opcdec fault instruction templates, formats, etc.
437##include "opcdec.isa"
438
439// Unimplemented instruction templates, formats, etc.
440##include "unimp.isa"
441
442// Unknown instruction templates, formats, etc.
443##include "unknown.isa"
444
445// Execution utility functions
446##include "util.isa"
447
448// The actual decoder
449##include "decoder.isa"