fp.isa (3953:300d526414e6) fp.isa (4172:141705d83494)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2005 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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41 /// Check "FP enabled" machine status bit. Called when executing any FP
42 /// instruction in full-system mode.
43 /// @retval Full-system mode: NoFault if FP is enabled, FenFault
44 /// if not. Non-full-system mode: always returns NoFault.
45#if FULL_SYSTEM
46 inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
47 {
48 Fault fault = NoFault; // dummy... this ipr access should not fault
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2005 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 32 unchanged lines hidden (view full) ---

41 /// Check "FP enabled" machine status bit. Called when executing any FP
42 /// instruction in full-system mode.
43 /// @retval Full-system mode: NoFault if FP is enabled, FenFault
44 /// if not. Non-full-system mode: always returns NoFault.
45#if FULL_SYSTEM
46 inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
47 {
48 Fault fault = NoFault; // dummy... this ipr access should not fault
49 if (!EV5::ICSR_FPE(xc->readMiscRegWithEffect(AlphaISA::IPR_ICSR))) {
49 if (!EV5::ICSR_FPE(xc->readMiscReg(AlphaISA::IPR_ICSR))) {
50 fault = new FloatEnableFault;
51 }
52 return fault;
53 }
54#else
55 inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
56 {
57 return NoFault;

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224 %(fp_enable_check)s;
225 %(op_decl)s;
226 %(op_rd)s;
227#if USE_FENV
228 if (roundingMode == Normal) {
229 %(code)s;
230 } else {
231 fesetround(getC99RoundingMode(
50 fault = new FloatEnableFault;
51 }
52 return fault;
53 }
54#else
55 inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
56 {
57 return NoFault;

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224 %(fp_enable_check)s;
225 %(op_decl)s;
226 %(op_rd)s;
227#if USE_FENV
228 if (roundingMode == Normal) {
229 %(code)s;
230 } else {
231 fesetround(getC99RoundingMode(
232 xc->readMiscReg(AlphaISA::MISCREG_FPCR)));
232 xc->readMiscRegNoEffect(AlphaISA::MISCREG_FPCR)));
233 %(code)s;
234 fesetround(FE_TONEAREST);
235 }
236#else
237 if (roundingMode != Normal && !warnedOnRounding) {
238 warn("%s: non-standard rounding mode not supported",
239 generateDisassembly(0, NULL));
240 warnedOnRounding = true;

--- 72 unchanged lines hidden --- 		233 %(code)s;
234 fesetround(FE_TONEAREST);
235 }
236#else
237 if (roundingMode != Normal && !warnedOnRounding) {
238 warn("%s: non-standard rounding mode not supported",
239 generateDisassembly(0, NULL));
240 warnedOnRounding = true;

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