decoder.isa (8901:bba76d164f9e) decoder.isa (9829:168e94599c2a)
1// -*- mode:c++ -*-
2
1// -*- mode:c++ -*-
2
3// Copyright (c) 2013 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
3// Copyright (c) 2003-2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright

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924
925 format BasicOperate {
926 // M5 special opcodes use the reserved 0x01 opcode space
927 0x01: decode M5FUNC {
928 0x00: arm({{
929 PseudoInst::arm(xc->tcBase());
930 }}, IsNonSpeculative);
931 0x01: quiesce({{
15// Copyright (c) 2003-2006 The Regents of The University of Michigan
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright

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936
937 format BasicOperate {
938 // M5 special opcodes use the reserved 0x01 opcode space
939 0x01: decode M5FUNC {
940 0x00: arm({{
941 PseudoInst::arm(xc->tcBase());
942 }}, IsNonSpeculative);
943 0x01: quiesce({{
932 PseudoInst::quiesce(xc->tcBase());
944 // Don't sleep if (unmasked) interrupts are pending
945 Interrupts* interrupts =
946 xc->tcBase()->getCpuPtr()->getInterruptController();
947 if (interrupts->checkInterrupts(xc->tcBase())) {
948 PseudoInst::quiesceSkip(xc->tcBase());
949 } else {
950 PseudoInst::quiesce(xc->tcBase());
951 }
933 }}, IsNonSpeculative, IsQuiesce);
934 0x02: quiesceNs({{
935 PseudoInst::quiesceNs(xc->tcBase(), R16);
936 }}, IsNonSpeculative, IsQuiesce);
937 0x03: quiesceCycles({{
938 PseudoInst::quiesceCycles(xc->tcBase(), R16);
939 }}, IsNonSpeculative, IsQuiesce, IsUnverifiable);
940 0x04: quiesceTime({{

--- 125 unchanged lines hidden --- 		952 }}, IsNonSpeculative, IsQuiesce);
953 0x02: quiesceNs({{
954 PseudoInst::quiesceNs(xc->tcBase(), R16);
955 }}, IsNonSpeculative, IsQuiesce);
956 0x03: quiesceCycles({{
957 PseudoInst::quiesceCycles(xc->tcBase(), R16);
958 }}, IsNonSpeculative, IsQuiesce, IsUnverifiable);
959 0x04: quiesceTime({{

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