decoder.isa (8588:ef28ed90449d) decoder.isa (8738:66bf413b0d5b)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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197 31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }});
198 }
199
200 // For IMPLVER, RA must be R31 and the B operand
201 // must be the immediate value 1.
202 0x6c: decode RA {
203 31: decode IMM {
204 1: decode INTIMM {
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 188 unchanged lines hidden (view full) ---

197 31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }});
198 }
199
200 // For IMPLVER, RA must be R31 and the B operand
201 // must be the immediate value 1.
202 0x6c: decode RA {
203 31: decode IMM {
204 1: decode INTIMM {
205 // return EV5 for FULL_SYSTEM and EV6 otherwise
206 1: implver({{ Rc = FULL_SYSTEM ? 1 : 2 }});
205 // return EV5 for FullSystem and EV6 otherwise
206 1: implver({{ Rc = FullSystem ? 1 : 2 }});
207 }
208 }
209 }
210
211 // The mysterious 11.25...
212 0x25: WarnUnimpl::eleven25();
213 }
214

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775 }
776
777 format BasicOperate {
778 0xc000: rpcc({{
779 /* Rb is a fake dependency so here is a fun way to get
780 * the parser to understand that.
781 */
782 uint64_t unused_var M5_VAR_USED = Rb;
207 }
208 }
209 }
210
211 // The mysterious 11.25...
212 0x25: WarnUnimpl::eleven25();
213 }
214

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775 }
776
777 format BasicOperate {
778 0xc000: rpcc({{
779 /* Rb is a fake dependency so here is a fun way to get
780 * the parser to understand that.
781 */
782 uint64_t unused_var M5_VAR_USED = Rb;
783 Ra = FULL_SYSTEM ? xc->readMiscReg(IPR_CC) : curTick();
783 Ra = FullSystem ? xc->readMiscReg(IPR_CC) : curTick();
784 }}, IsUnverifiable);
785
786 // All of the barrier instructions below do nothing in
787 // their execute() methods (hence the empty code blocks).
788 // All of their functionality is hard-coded in the
789 // pipeline based on the flags IsSerializing,
790 // IsMemBarrier, and IsWriteBarrier. In the current
791 // detailed CPU model, the execute() function only gets

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800 // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
801 // them the same though.
802 0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
803 0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
804 0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
805 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
806 }
807
784 }}, IsUnverifiable);
785
786 // All of the barrier instructions below do nothing in
787 // their execute() methods (hence the empty code blocks).
788 // All of their functionality is hard-coded in the
789 // pipeline based on the flags IsSerializing,
790 // IsMemBarrier, and IsWriteBarrier. In the current
791 // detailed CPU model, the execute() function only gets

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800 // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
801 // them the same though.
802 0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
803 0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
804 0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
805 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
806 }
807
808 0xe000: decode FULL_SYSTEM {
808 0xe000: decode FullSystem {
809 0: FailUnimpl::rc_se();
810 default: BasicOperate::rc({{
811 Ra = IntrFlag;
812 IntrFlag = 0;
813 }}, IsNonSpeculative, IsUnverifiable);
814 }
809 0: FailUnimpl::rc_se();
810 default: BasicOperate::rc({{
811 Ra = IntrFlag;
812 IntrFlag = 0;
813 }}, IsNonSpeculative, IsUnverifiable);
814 }
815 0xf000: decode FULL_SYSTEM {
815 0xf000: decode FullSystem {
816 0: FailUnimpl::rs_se();
817 default: BasicOperate::rs({{
818 Ra = IntrFlag;
819 IntrFlag = 1;
820 }}, IsNonSpeculative, IsUnverifiable);
821 }
822 }
823

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817 default: BasicOperate::rs({{
818 Ra = IntrFlag;
819 IntrFlag = 1;
820 }}, IsNonSpeculative, IsUnverifiable);
821 }
822 }
823

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