decoder.isa (8556:2afd82e84d95) decoder.isa (8560:5c4bac827934)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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198 }
199
200 // For IMPLVER, RA must be R31 and the B operand
201 // must be the immediate value 1.
202 0x6c: decode RA {
203 31: decode IMM {
204 1: decode INTIMM {
205 // return EV5 for FULL_SYSTEM and EV6 otherwise
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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198 }
199
200 // For IMPLVER, RA must be R31 and the B operand
201 // must be the immediate value 1.
202 0x6c: decode RA {
203 31: decode IMM {
204 1: decode INTIMM {
205 // return EV5 for FULL_SYSTEM and EV6 otherwise
206 1: implver({{
207#if FULL_SYSTEM
208 Rc = 1;
209#else
210 Rc = 2;
211#endif
212 }});
206 1: implver({{ Rc = FULL_SYSTEM ? 1 : 2 }});
213 }
214 }
215 }
216
207 }
208 }
209 }
210
217#if FULL_SYSTEM
218 // The mysterious 11.25...
219 0x25: WarnUnimpl::eleven25();
211 // The mysterious 11.25...
212 0x25: WarnUnimpl::eleven25();
220#endif
221 }
222
223 0x12: decode INTFUNC {
224 0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
225 0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }});
226 0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }});
227
228 0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});

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779 format MiscPrefetch {
780 0xf800: wh64({{ EA = Rb & ~ULL(63); }},
781 {{ ; }},
782 mem_flags = PREFETCH);
783 }
784
785 format BasicOperate {
786 0xc000: rpcc({{
213 }
214
215 0x12: decode INTFUNC {
216 0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
217 0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }});
218 0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }});
219
220 0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});

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771 format MiscPrefetch {
772 0xf800: wh64({{ EA = Rb & ~ULL(63); }},
773 {{ ; }},
774 mem_flags = PREFETCH);
775 }
776
777 format BasicOperate {
778 0xc000: rpcc({{
787#if FULL_SYSTEM
788 /* Rb is a fake dependency so here is a fun way to get
789 * the parser to understand that.
790 */
791 Ra = xc->readMiscReg(IPR_CC) + (Rb & 0);
792
793#else
794 Ra = curTick();
795#endif
779 /* Rb is a fake dependency so here is a fun way to get
780 * the parser to understand that.
781 */
782 uint64_t unused_var M5_VAR_USED = Rb;
783 Ra = FULL_SYSTEM ? xc->readMiscReg(IPR_CC) : curTick();
796 }}, IsUnverifiable);
797
798 // All of the barrier instructions below do nothing in
799 // their execute() methods (hence the empty code blocks).
800 // All of their functionality is hard-coded in the
801 // pipeline based on the flags IsSerializing,
802 // IsMemBarrier, and IsWriteBarrier. In the current
803 // detailed CPU model, the execute() function only gets

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812 // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
813 // them the same though.
814 0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
815 0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
816 0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
817 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
818 }
819
784 }}, IsUnverifiable);
785
786 // All of the barrier instructions below do nothing in
787 // their execute() methods (hence the empty code blocks).
788 // All of their functionality is hard-coded in the
789 // pipeline based on the flags IsSerializing,
790 // IsMemBarrier, and IsWriteBarrier. In the current
791 // detailed CPU model, the execute() function only gets

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800 // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
801 // them the same though.
802 0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
803 0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
804 0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
805 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
806 }
807
820#if FULL_SYSTEM
821 format BasicOperate {
822 0xe000: rc({{
808 0xe000: decode FULL_SYSTEM {
809 0: FailUnimpl::rc_se();
810 default: BasicOperate::rc({{
823 Ra = IntrFlag;
824 IntrFlag = 0;
825 }}, IsNonSpeculative, IsUnverifiable);
811 Ra = IntrFlag;
812 IntrFlag = 0;
813 }}, IsNonSpeculative, IsUnverifiable);
826 0xf000: rs({{
814 }
815 0xf000: decode FULL_SYSTEM {
816 0: FailUnimpl::rs_se();
817 default: BasicOperate::rs({{
827 Ra = IntrFlag;
828 IntrFlag = 1;
829 }}, IsNonSpeculative, IsUnverifiable);
830 }
818 Ra = IntrFlag;
819 IntrFlag = 1;
820 }}, IsNonSpeculative, IsUnverifiable);
821 }
831#else
832 format FailUnimpl {
833 0xe000: rc();
834 0xf000: rs();
835 }
836#endif
837 }
838
839#if FULL_SYSTEM
840 0x00: CallPal::call_pal({{
841 if (!palValid ||
842 (palPriv
843 && xc->readMiscReg(IPR_ICM) != mode_kernel)) {
844 // invalid pal function code, or attempt to do privileged

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823
824#if FULL_SYSTEM
825 0x00: CallPal::call_pal({{
826 if (!palValid ||
827 (palPriv
828 && xc->readMiscReg(IPR_ICM) != mode_kernel)) {
829 // invalid pal function code, or attempt to do privileged

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