decoder.isa (5952:c1ee8282291d) decoder.isa (6076:e141cc7896ce)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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40 0x09: ldah({{ Ra = Rb + (disp << 16); }});
41 }
42
43 format LoadOrNop {
44 0x0a: ldbu({{ Ra.uq = Mem.ub; }});
45 0x0c: ldwu({{ Ra.uq = Mem.uw; }});
46 0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }});
47 0x23: ldt({{ Fa = Mem.df; }});
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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40 0x09: ldah({{ Ra = Rb + (disp << 16); }});
41 }
42
43 format LoadOrNop {
44 0x0a: ldbu({{ Ra.uq = Mem.ub; }});
45 0x0c: ldwu({{ Ra.uq = Mem.uw; }});
46 0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }});
47 0x23: ldt({{ Fa = Mem.df; }});
48 0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LOCKED);
49 0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LOCKED);
48 0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LLSC);
49 0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LLSC);
50#ifdef USE_COPY
51 0x20: MiscPrefetch::copy_load({{ EA = Ra; }},
52 {{ fault = xc->copySrcTranslate(EA); }},
53 inst_flags = [IsMemRef, IsLoad, IsCopy]);
54#endif
55 }
56
57 format LoadOrPrefetch {

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82 0x2e: stl_c({{ Mem.ul = Ra<31:0>; }},
83 {{
84 uint64_t tmp = write_result;
85 // see stq_c
86 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
87 if (tmp == 1) {
88 xc->setStCondFailures(0);
89 }
50#ifdef USE_COPY
51 0x20: MiscPrefetch::copy_load({{ EA = Ra; }},
52 {{ fault = xc->copySrcTranslate(EA); }},
53 inst_flags = [IsMemRef, IsLoad, IsCopy]);
54#endif
55 }
56
57 format LoadOrPrefetch {

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82 0x2e: stl_c({{ Mem.ul = Ra<31:0>; }},
83 {{
84 uint64_t tmp = write_result;
85 // see stq_c
86 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
87 if (tmp == 1) {
88 xc->setStCondFailures(0);
89 }
90 }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
90 }}, mem_flags = LLSC, inst_flags = IsStoreConditional);
91 0x2f: stq_c({{ Mem.uq = Ra; }},
92 {{
93 uint64_t tmp = write_result;
94 // If the write operation returns 0 or 1, then
95 // this was a conventional store conditional,
96 // and the value indicates the success/failure
97 // of the operation. If another value is
98 // returned, then this was a Turbolaser
99 // mailbox access, and we don't update the
100 // result register at all.
101 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
102 if (tmp == 1) {
103 // clear failure counter... this is
104 // non-architectural and for debugging
105 // only.
106 xc->setStCondFailures(0);
107 }
91 0x2f: stq_c({{ Mem.uq = Ra; }},
92 {{
93 uint64_t tmp = write_result;
94 // If the write operation returns 0 or 1, then
95 // this was a conventional store conditional,
96 // and the value indicates the success/failure
97 // of the operation. If another value is
98 // returned, then this was a Turbolaser
99 // mailbox access, and we don't update the
100 // result register at all.
101 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
102 if (tmp == 1) {
103 // clear failure counter... this is
104 // non-architectural and for debugging
105 // only.
106 xc->setStCondFailures(0);
107 }
108 }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
108 }}, mem_flags = LLSC, inst_flags = IsStoreConditional);
109 }
110
111 format IntegerOperate {
112
113 0x10: decode INTFUNC { // integer arithmetic operations
114
115 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
116 0x40: addlv({{

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110
111 format IntegerOperate {
112
113 0x10: decode INTFUNC { // integer arithmetic operations
114
115 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
116 0x40: addlv({{

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