decoder.isa (5640:c811ced9efc1) decoder.isa (5702:bf84e2fa05f7)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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693 && xc->readMiscReg(IPR_ICM) != mode_kernel)) {
694 // invalid pal function code, or attempt to do privileged
695 // PAL call in non-kernel mode
696 fault = new UnimplementedOpcodeFault;
697 }
698 else {
699 // check to see if simulator wants to do something special
700 // on this PAL call (including maybe suppress it)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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693 && xc->readMiscReg(IPR_ICM) != mode_kernel)) {
694 // invalid pal function code, or attempt to do privileged
695 // PAL call in non-kernel mode
696 fault = new UnimplementedOpcodeFault;
697 }
698 else {
699 // check to see if simulator wants to do something special
700 // on this PAL call (including maybe suppress it)
701
702 bool dopal = true;
701 bool dopal = xc->simPalCheck(palFunc);
703
702
704 ThreadContext * tc = xc->tcBase();
705 AlphaISA::Kernel::Statistics * kernelStats = tc->getKernelStats();
706 System * system = tc->getSystemPtr();
707 if (kernelStats)
708 kernelStats->callpal(palFunc, tc);
709
710 switch (palFunc) {
711 case PAL::halt:
712 tc->halt();
713 if (--System::numSystemsRunning == 0)
714 exitSimLoop("all cpus halted");
715 break;
716
717 case PAL::bpt:
718 case PAL::bugchk:
719 if (system->breakpoint())
720 dopal = false;
721 break;
722 }
723
724 if (dopal) {
725 xc->setMiscReg(IPR_EXC_ADDR, NPC);
726 NPC = xc->readMiscReg(IPR_PAL_BASE) + palOffset;
727 }
728 }
729 }}, IsNonSpeculative);
730#else
731 0x00: decode PALFUNC {

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802 if (traceData) { traceData->setData(Ra); }
803 }}, IsIprAccess);
804 }
805 }
806
807 format BasicOperate {
808 0x1e: decode PALMODE {
809 0: OpcdecFault::hw_rei();
703 if (dopal) {
704 xc->setMiscReg(IPR_EXC_ADDR, NPC);
705 NPC = xc->readMiscReg(IPR_PAL_BASE) + palOffset;
706 }
707 }
708 }}, IsNonSpeculative);
709#else
710 0x00: decode PALFUNC {

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781 if (traceData) { traceData->setData(Ra); }
782 }}, IsIprAccess);
783 }
784 }
785
786 format BasicOperate {
787 0x1e: decode PALMODE {
788 0: OpcdecFault::hw_rei();
810 1: hw_rei({{
811 NPC = ExcAddr;
812 ThreadContext * tc = xc->tcBase();
813 if (!tc->misspeculating()) {
814 AlphaISA::Kernel::Statistics * kernelStats =
815 tc->getKernelStats();
816 if (kernelStats)
817 kernelStats->hwrei();
818 }
819 }}, IsSerializing, IsSerializeBefore);
789 1:hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
820 }
821
822 // M5 special opcodes use the reserved 0x01 opcode space
823 0x01: decode M5FUNC {
824 0x00: arm({{
825 PseudoInst::arm(xc->tcBase());
826 }}, IsNonSpeculative);
827 0x01: quiesce({{

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791
792 // M5 special opcodes use the reserved 0x01 opcode space
793 0x01: decode M5FUNC {
794 0x00: arm({{
795 PseudoInst::arm(xc->tcBase());
796 }}, IsNonSpeculative);
797 0x01: quiesce({{

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