decoder.isa (5568:d14250d688d2) decoder.isa (5639:67cc7f0427e7)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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781 if (traceData) { traceData->setData(Ra); }
782 }}, IsIprAccess);
783 }
784 }
785
786 format BasicOperate {
787 0x1e: decode PALMODE {
788 0: OpcdecFault::hw_rei();
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 772 unchanged lines hidden (view full) ---

781 if (traceData) { traceData->setData(Ra); }
782 }}, IsIprAccess);
783 }
784 }
785
786 format BasicOperate {
787 0x1e: decode PALMODE {
788 0: OpcdecFault::hw_rei();
789 1:hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
789 1: hw_rei({{
790 NPC = ExcAddr;
791 ThreadContext * tc = xc->tcBase();
792 if (!tc->misspeculating()) {
793 AlphaISA::Kernel::Statistics * kernelStats =
794 tc->getKernelStats();
795 if (kernelStats)
796 kernelStats->hwrei();
797 }
798 }}, IsSerializing, IsSerializeBefore);
790 }
791
792 // M5 special opcodes use the reserved 0x01 opcode space
793 0x01: decode M5FUNC {
794 0x00: arm({{
795 PseudoInst::arm(xc->tcBase());
796 }}, IsNonSpeculative);
797 0x01: quiesce({{

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800
801 // M5 special opcodes use the reserved 0x01 opcode space
802 0x01: decode M5FUNC {
803 0x00: arm({{
804 PseudoInst::arm(xc->tcBase());
805 }}, IsNonSpeculative);
806 0x01: quiesce({{

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