decoder.isa (4828:768d4cf6b0dc) | decoder.isa (5505:90d6811d5ea6) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2003-2006 The Regents of The University of Michigan 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 792 unchanged lines hidden (view full) --- 801 PseudoInst::quiesceNs(xc->tcBase(), R16); 802 }}, IsNonSpeculative, IsQuiesce); 803 0x03: quiesceCycles({{ 804 PseudoInst::quiesceCycles(xc->tcBase(), R16); 805 }}, IsNonSpeculative, IsQuiesce, IsUnverifiable); 806 0x04: quiesceTime({{ 807 R0 = PseudoInst::quiesceTime(xc->tcBase()); 808 }}, IsNonSpeculative, IsUnverifiable); | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2003-2006 The Regents of The University of Michigan 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 792 unchanged lines hidden (view full) --- 801 PseudoInst::quiesceNs(xc->tcBase(), R16); 802 }}, IsNonSpeculative, IsQuiesce); 803 0x03: quiesceCycles({{ 804 PseudoInst::quiesceCycles(xc->tcBase(), R16); 805 }}, IsNonSpeculative, IsQuiesce, IsUnverifiable); 806 0x04: quiesceTime({{ 807 R0 = PseudoInst::quiesceTime(xc->tcBase()); 808 }}, IsNonSpeculative, IsUnverifiable); |
809 0x10: ivlb({{ 810 warn_once("Obsolete M5 instruction ivlb encountered.\n"); | 809 0x10: deprecated_ivlb({{ 810 warn_once("Obsolete M5 ivlb instruction encountered.\n"); |
811 }}); | 811 }}); |
812 0x11: ivle({{ 813 warn_once("Obsolete M5 instruction ivlb encountered.\n"); | 812 0x11: deprecated_ivle({{ 813 warn_once("Obsolete M5 ivlb instruction encountered.\n"); |
814 }}); | 814 }}); |
815 0x20: m5exit_old({{ 816 PseudoInst::m5exit_old(xc->tcBase()); | 815 0x20: deprecated_exit ({{ 816 warn_once("deprecated M5 exit instruction encountered.\n"); 817 PseudoInst::m5exit(xc->tcBase(), 0); |
817 }}, No_OpClass, IsNonSpeculative); 818 0x21: m5exit({{ 819 PseudoInst::m5exit(xc->tcBase(), R16); 820 }}, No_OpClass, IsNonSpeculative); 821 0x31: loadsymbol({{ 822 PseudoInst::loadsymbol(xc->tcBase()); 823 }}, No_OpClass, IsNonSpeculative); | 818 }}, No_OpClass, IsNonSpeculative); 819 0x21: m5exit({{ 820 PseudoInst::m5exit(xc->tcBase(), R16); 821 }}, No_OpClass, IsNonSpeculative); 822 0x31: loadsymbol({{ 823 PseudoInst::loadsymbol(xc->tcBase()); 824 }}, No_OpClass, IsNonSpeculative); |
824 0x30: initparam({{ Ra = xc->tcBase()->getCpuPtr()->system->init_param; }}); | 825 0x30: initparam({{ 826 Ra = xc->tcBase()->getCpuPtr()->system->init_param; 827 }}); |
825 0x40: resetstats({{ 826 PseudoInst::resetstats(xc->tcBase(), R16, R17); 827 }}, IsNonSpeculative); 828 0x41: dumpstats({{ 829 PseudoInst::dumpstats(xc->tcBase(), R16, R17); 830 }}, IsNonSpeculative); 831 0x42: dumpresetstats({{ 832 PseudoInst::dumpresetstats(xc->tcBase(), R16, R17); --- 11 unchanged lines hidden (view full) --- 844 PseudoInst::switchcpu(xc->tcBase()); 845 }}, IsNonSpeculative); 846 0x53: m5addsymbol({{ 847 PseudoInst::addsymbol(xc->tcBase(), R16, R17); 848 }}, IsNonSpeculative); 849 0x54: m5panic({{ 850 panic("M5 panic instruction called at pc=%#x.", xc->readPC()); 851 }}, IsNonSpeculative); | 828 0x40: resetstats({{ 829 PseudoInst::resetstats(xc->tcBase(), R16, R17); 830 }}, IsNonSpeculative); 831 0x41: dumpstats({{ 832 PseudoInst::dumpstats(xc->tcBase(), R16, R17); 833 }}, IsNonSpeculative); 834 0x42: dumpresetstats({{ 835 PseudoInst::dumpresetstats(xc->tcBase(), R16, R17); --- 11 unchanged lines hidden (view full) --- 847 PseudoInst::switchcpu(xc->tcBase()); 848 }}, IsNonSpeculative); 849 0x53: m5addsymbol({{ 850 PseudoInst::addsymbol(xc->tcBase(), R16, R17); 851 }}, IsNonSpeculative); 852 0x54: m5panic({{ 853 panic("M5 panic instruction called at pc=%#x.", xc->readPC()); 854 }}, IsNonSpeculative); |
852 0x55: m5anBegin({{ 853 PseudoInst::anBegin(xc->tcBase(), R16); | 855 0x55: m5reserved1({{ 856 warn("M5 reserved opcode ignored"); |
854 }}, IsNonSpeculative); | 857 }}, IsNonSpeculative); |
855 0x56: m5anWait({{ 856 PseudoInst::anWait(xc->tcBase(), R16, R17); | 858 0x56: m5reserved2({{ 859 warn("M5 reserved opcode ignored"); |
857 }}, IsNonSpeculative); | 860 }}, IsNonSpeculative); |
861 0x57: m5reserved3({{ 862 warn("M5 reserved opcode ignored"); 863 }}, IsNonSpeculative); 864 0x58: m5reserved4({{ 865 warn("M5 reserved opcode ignored"); 866 }}, IsNonSpeculative); 867 0x59: m5reserved5({{ 868 warn("M5 reserved opcode ignored"); 869 }}, IsNonSpeculative); |
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858 } 859 } 860#endif 861} | 870 } 871 } 872#endif 873} |