decoder.isa (4027:53292b42ee1c) decoder.isa (4036:bd6473d8fe70)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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79 }
80
81 format StoreCond {
82 0x2e: stl_c({{ Mem.ul = Ra<31:0>; }},
83 {{
84 uint64_t tmp = write_result;
85 // see stq_c
86 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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79 }
80
81 format StoreCond {
82 0x2e: stl_c({{ Mem.ul = Ra<31:0>; }},
83 {{
84 uint64_t tmp = write_result;
85 // see stq_c
86 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
87 if (tmp == 1) {
88 xc->setStCondFailures(0);
89 }
90 }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
91 0x2f: stq_c({{ Mem.uq = Ra; }},
92 {{
93 uint64_t tmp = write_result;
94 // If the write operation returns 0 or 1, then
95 // this was a conventional store conditional,
96 // and the value indicates the success/failure
97 // of the operation. If another value is
98 // returned, then this was a Turbolaser
99 // mailbox access, and we don't update the
100 // result register at all.
101 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
87 }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
88 0x2f: stq_c({{ Mem.uq = Ra; }},
89 {{
90 uint64_t tmp = write_result;
91 // If the write operation returns 0 or 1, then
92 // this was a conventional store conditional,
93 // and the value indicates the success/failure
94 // of the operation. If another value is
95 // returned, then this was a Turbolaser
96 // mailbox access, and we don't update the
97 // result register at all.
98 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
102 if (tmp == 1) {
103 // clear failure counter... this is
104 // non-architectural and for debugging
105 // only.
106 xc->setStCondFailures(0);
107 }
108 }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
109 }
110
111 format IntegerOperate {
112
113 0x10: decode INTFUNC { // integer arithmetic operations
114
115 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});

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723 }
724#endif
725
726#if FULL_SYSTEM
727 0x1b: decode PALMODE {
728 0: OpcdecFault::hw_st_quad();
729 1: decode HW_LDST_QUAD {
730 format HwLoad {
99 }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
100 }
101
102 format IntegerOperate {
103
104 0x10: decode INTFUNC { // integer arithmetic operations
105
106 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});

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714 }
715#endif
716
717#if FULL_SYSTEM
718 0x1b: decode PALMODE {
719 0: OpcdecFault::hw_st_quad();
720 1: decode HW_LDST_QUAD {
721 format HwLoad {
731 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L);
732 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q);
722 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }},
723 L, IsSerializing, IsSerializeBefore);
724 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }},
725 Q, IsSerializing, IsSerializeBefore);
733 }
734 }
735 }
736
737 0x1f: decode PALMODE {
738 0: OpcdecFault::hw_st_cond();
739 format HwStore {
740 1: decode HW_LDST_COND {
741 0: decode HW_LDST_QUAD {
742 0: hw_st({{ EA = (Rb + disp) & ~3; }},
726 }
727 }
728 }
729
730 0x1f: decode PALMODE {
731 0: OpcdecFault::hw_st_cond();
732 format HwStore {
733 1: decode HW_LDST_COND {
734 0: decode HW_LDST_QUAD {
735 0: hw_st({{ EA = (Rb + disp) & ~3; }},
743 {{ Mem.ul = Ra<31:0>; }}, L);
736 {{ Mem.ul = Ra<31:0>; }}, L, IsSerializing, IsSerializeBefore);
744 1: hw_st({{ EA = (Rb + disp) & ~7; }},
737 1: hw_st({{ EA = (Rb + disp) & ~7; }},
745 {{ Mem.uq = Ra.uq; }}, Q);
738 {{ Mem.uq = Ra.uq; }}, Q, IsSerializing, IsSerializeBefore);
746 }
747
748 1: FailUnimpl::hw_st_cond();
749 }
750 }
751 }
752
753 0x19: decode PALMODE {

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740
741 1: FailUnimpl::hw_st_cond();
742 }
743 }
744 }
745
746 0x19: decode PALMODE {

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