decoder.isa (3680:00bf1ba79520) decoder.isa (4027:53292b42ee1c)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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79 }
80
81 format StoreCond {
82 0x2e: stl_c({{ Mem.ul = Ra<31:0>; }},
83 {{
84 uint64_t tmp = write_result;
85 // see stq_c
86 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 70 unchanged lines hidden (view full) ---

79 }
80
81 format StoreCond {
82 0x2e: stl_c({{ Mem.ul = Ra<31:0>; }},
83 {{
84 uint64_t tmp = write_result;
85 // see stq_c
86 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
87 if (tmp == 1) {
88 xc->setStCondFailures(0);
89 }
87 }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
88 0x2f: stq_c({{ Mem.uq = Ra; }},
89 {{
90 uint64_t tmp = write_result;
91 // If the write operation returns 0 or 1, then
92 // this was a conventional store conditional,
93 // and the value indicates the success/failure
94 // of the operation. If another value is
95 // returned, then this was a Turbolaser
96 // mailbox access, and we don't update the
97 // result register at all.
98 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
90 }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
91 0x2f: stq_c({{ Mem.uq = Ra; }},
92 {{
93 uint64_t tmp = write_result;
94 // If the write operation returns 0 or 1, then
95 // this was a conventional store conditional,
96 // and the value indicates the success/failure
97 // of the operation. If another value is
98 // returned, then this was a Turbolaser
99 // mailbox access, and we don't update the
100 // result register at all.
101 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
102 if (tmp == 1) {
103 // clear failure counter... this is
104 // non-architectural and for debugging
105 // only.
106 xc->setStCondFailures(0);
107 }
99 }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
100 }
101
102 format IntegerOperate {
103
104 0x10: decode INTFUNC { // integer arithmetic operations
105
106 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});

--- 744 unchanged lines hidden --- 		108 }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
109 }
110
111 format IntegerOperate {
112
113 0x10: decode INTFUNC { // integer arithmetic operations
114
115 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});

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