decoder.isa (3089:0ea2eb13c4de) decoder.isa (3125:febd811bccc6)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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774 0x01: quiesce({{
775 AlphaPseudo::quiesce(xc->tcBase());
776 }}, IsNonSpeculative, IsQuiesce);
777 0x02: quiesceNs({{
778 AlphaPseudo::quiesceNs(xc->tcBase(), R16);
779 }}, IsNonSpeculative, IsQuiesce);
780 0x03: quiesceCycles({{
781 AlphaPseudo::quiesceCycles(xc->tcBase(), R16);
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 765 unchanged lines hidden (view full) ---

774 0x01: quiesce({{
775 AlphaPseudo::quiesce(xc->tcBase());
776 }}, IsNonSpeculative, IsQuiesce);
777 0x02: quiesceNs({{
778 AlphaPseudo::quiesceNs(xc->tcBase(), R16);
779 }}, IsNonSpeculative, IsQuiesce);
780 0x03: quiesceCycles({{
781 AlphaPseudo::quiesceCycles(xc->tcBase(), R16);
782 }}, IsNonSpeculative, IsQuiesce);
782 }}, IsNonSpeculative, IsQuiesce, IsUnverifiable);
783 0x04: quiesceTime({{
784 R0 = AlphaPseudo::quiesceTime(xc->tcBase());
783 0x04: quiesceTime({{
784 R0 = AlphaPseudo::quiesceTime(xc->tcBase());
785 }}, IsNonSpeculative);
785 }}, IsNonSpeculative, IsUnverifiable);
786 0x10: ivlb({{
787 AlphaPseudo::ivlb(xc->tcBase());
788 }}, No_OpClass, IsNonSpeculative);
789 0x11: ivle({{
790 AlphaPseudo::ivle(xc->tcBase());
791 }}, No_OpClass, IsNonSpeculative);
792 0x20: m5exit_old({{
793 AlphaPseudo::m5exit_old(xc->tcBase());
794 }}, No_OpClass, IsNonSpeculative);
795 0x21: m5exit({{
796 AlphaPseudo::m5exit(xc->tcBase(), R16);
797 }}, No_OpClass, IsNonSpeculative);
786 0x10: ivlb({{
787 AlphaPseudo::ivlb(xc->tcBase());
788 }}, No_OpClass, IsNonSpeculative);
789 0x11: ivle({{
790 AlphaPseudo::ivle(xc->tcBase());
791 }}, No_OpClass, IsNonSpeculative);
792 0x20: m5exit_old({{
793 AlphaPseudo::m5exit_old(xc->tcBase());
794 }}, No_OpClass, IsNonSpeculative);
795 0x21: m5exit({{
796 AlphaPseudo::m5exit(xc->tcBase(), R16);
797 }}, No_OpClass, IsNonSpeculative);
798 0x31: loadsymbol({{
799 AlphaPseudo::loadsymbol(xc->tcBase());
800 }}, No_OpClass, IsNonSpeculative);
798 0x30: initparam({{ Ra = xc->tcBase()->getCpuPtr()->system->init_param; }});
799 0x40: resetstats({{
800 AlphaPseudo::resetstats(xc->tcBase(), R16, R17);
801 }}, IsNonSpeculative);
802 0x41: dumpstats({{
803 AlphaPseudo::dumpstats(xc->tcBase(), R16, R17);
804 }}, IsNonSpeculative);
805 0x42: dumpresetstats({{

--- 30 unchanged lines hidden --- 		801 0x30: initparam({{ Ra = xc->tcBase()->getCpuPtr()->system->init_param; }});
802 0x40: resetstats({{
803 AlphaPseudo::resetstats(xc->tcBase(), R16, R17);
804 }}, IsNonSpeculative);
805 0x41: dumpstats({{
806 AlphaPseudo::dumpstats(xc->tcBase(), R16, R17);
807 }}, IsNonSpeculative);
808 0x42: dumpresetstats({{

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