decoder.isa (2654:9559cfa91b9d) decoder.isa (2665:a124942bacb8)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Steve Reinhardt
28
29////////////////////////////////////////////////////////////////////
30//
31// The actual decoder specification
32//
33
34decode OPCODE default Unknown::unknown() {
35

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73 }
74
75 format StoreCond {
76 0x2e: stl_c({{ Mem.ul = Ra<31:0>; }},
77 {{
78 uint64_t tmp = write_result;
79 // see stq_c
80 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
30
31////////////////////////////////////////////////////////////////////
32//
33// The actual decoder specification
34//
35
36decode OPCODE default Unknown::unknown() {
37

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75 }
76
77 format StoreCond {
78 0x2e: stl_c({{ Mem.ul = Ra<31:0>; }},
79 {{
80 uint64_t tmp = write_result;
81 // see stq_c
82 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
81 }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
83 }}, mem_flags = LOCKED);
82 0x2f: stq_c({{ Mem.uq = Ra; }},
83 {{
84 uint64_t tmp = write_result;
85 // If the write operation returns 0 or 1, then
86 // this was a conventional store conditional,
87 // and the value indicates the success/failure
88 // of the operation. If another value is
89 // returned, then this was a Turbolaser
90 // mailbox access, and we don't update the
91 // result register at all.
92 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
84 0x2f: stq_c({{ Mem.uq = Ra; }},
85 {{
86 uint64_t tmp = write_result;
87 // If the write operation returns 0 or 1, then
88 // this was a conventional store conditional,
89 // and the value indicates the success/failure
90 // of the operation. If another value is
91 // returned, then this was a Turbolaser
92 // mailbox access, and we don't update the
93 // result register at all.
94 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
93 }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
95 }}, mem_flags = LOCKED);
94 }
95
96 format IntegerOperate {
97
98 0x10: decode INTFUNC { // integer arithmetic operations
99
100 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
101 0x40: addlv({{

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591
592 0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
593 0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }});
594 0x02c: fcmovlt({{ Fc = (Fa < 0) ? Fb : Fc; }});
595 0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }});
596 0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
597 0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }});
598
96 }
97
98 format IntegerOperate {
99
100 0x10: decode INTFUNC { // integer arithmetic operations
101
102 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
103 0x40: addlv({{

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593
594 0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
595 0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }});
596 0x02c: fcmovlt({{ Fc = (Fa < 0) ? Fb : Fc; }});
597 0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }});
598 0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
599 0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }});
600
599 0x024: mt_fpcr({{ FPCR = Fa.uq; }}, IsIprAccess);
600 0x025: mf_fpcr({{ Fa.uq = FPCR; }}, IsIprAccess);
601 0x024: mt_fpcr({{ FPCR = Fa.uq; }});
602 0x025: mf_fpcr({{ Fa.uq = FPCR; }});
601 }
602 }
603
604 // miscellaneous mem-format ops
605 0x18: decode MEMFUNC {
606 format WarnUnimpl {
607 0x8000: fetch();
608 0xa000: fetch_m();

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623 /* Rb is a fake dependency so here is a fun way to get
624 * the parser to understand that.
625 */
626 Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC, fault) + (Rb & 0);
627
628#else
629 Ra = curTick;
630#endif
603 }
604 }
605
606 // miscellaneous mem-format ops
607 0x18: decode MEMFUNC {
608 format WarnUnimpl {
609 0x8000: fetch();
610 0xa000: fetch_m();

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625 /* Rb is a fake dependency so here is a fun way to get
626 * the parser to understand that.
627 */
628 Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC, fault) + (Rb & 0);
629
630#else
631 Ra = curTick;
632#endif
631 }}, IsUnverifiable);
633 }});
632
633 // All of the barrier instructions below do nothing in
634 // their execute() methods (hence the empty code blocks).
635 // All of their functionality is hard-coded in the
636 // pipeline based on the flags IsSerializing,
637 // IsMemBarrier, and IsWriteBarrier. In the current
638 // detailed CPU model, the execute() function only gets
639 // called at fetch, so there's no way to generate pipeline
640 // behavior at any other stage. Once we go to an
641 // exec-in-exec CPU model we should be able to get rid of
642 // these flags and implement this behavior via the
643 // execute() methods.
644
645 // trapb is just a barrier on integer traps, where excb is
646 // a barrier on integer and FP traps. "EXCB is thus a
647 // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
648 // them the same though.
634
635 // All of the barrier instructions below do nothing in
636 // their execute() methods (hence the empty code blocks).
637 // All of their functionality is hard-coded in the
638 // pipeline based on the flags IsSerializing,
639 // IsMemBarrier, and IsWriteBarrier. In the current
640 // detailed CPU model, the execute() function only gets
641 // called at fetch, so there's no way to generate pipeline
642 // behavior at any other stage. Once we go to an
643 // exec-in-exec CPU model we should be able to get rid of
644 // these flags and implement this behavior via the
645 // execute() methods.
646
647 // trapb is just a barrier on integer traps, where excb is
648 // a barrier on integer and FP traps. "EXCB is thus a
649 // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
650 // them the same though.
649 0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
650 0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
651 0x0000: trapb({{ }}, IsSerializing, No_OpClass);
652 0x0400: excb({{ }}, IsSerializing, No_OpClass);
651 0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
652 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
653 }
654
655#if FULL_SYSTEM
656 format BasicOperate {
657 0xe000: rc({{
658 Ra = xc->readIntrFlag();

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696 format EmulatedCallPal {
697 0x00: halt ({{
698 SimExit(curTick, "halt instruction encountered");
699 }}, IsNonSpeculative);
700 0x83: callsys({{
701 xc->syscall(R0);
702 }}, IsNonSpeculative);
703 // Read uniq reg into ABI return value register (r0)
653 0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
654 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
655 }
656
657#if FULL_SYSTEM
658 format BasicOperate {
659 0xe000: rc({{
660 Ra = xc->readIntrFlag();

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698 format EmulatedCallPal {
699 0x00: halt ({{
700 SimExit(curTick, "halt instruction encountered");
701 }}, IsNonSpeculative);
702 0x83: callsys({{
703 xc->syscall(R0);
704 }}, IsNonSpeculative);
705 // Read uniq reg into ABI return value register (r0)
704 0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
706 0x9e: rduniq({{ R0 = Runiq; }});
705 // Write uniq reg with value from ABI arg register (r16)
707 // Write uniq reg with value from ABI arg register (r16)
706 0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess);
708 0x9f: wruniq({{ Runiq = R16; }});
707 }
708 }
709#endif
710
711#if FULL_SYSTEM
712 0x1b: decode PALMODE {
713 0: OpcdecFault::hw_st_quad();
714 1: decode HW_LDST_QUAD {

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735 }
736 }
737
738 0x19: decode PALMODE {
739 0: OpcdecFault::hw_mfpr();
740 format HwMoveIPR {
741 1: hw_mfpr({{
742 Ra = xc->readMiscRegWithEffect(ipr_index, fault);
709 }
710 }
711#endif
712
713#if FULL_SYSTEM
714 0x1b: decode PALMODE {
715 0: OpcdecFault::hw_st_quad();
716 1: decode HW_LDST_QUAD {

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737 }
738 }
739
740 0x19: decode PALMODE {
741 0: OpcdecFault::hw_mfpr();
742 format HwMoveIPR {
743 1: hw_mfpr({{
744 Ra = xc->readMiscRegWithEffect(ipr_index, fault);
743 }}, IsIprAccess);
745 }});
744 }
745 }
746
747 0x1d: decode PALMODE {
748 0: OpcdecFault::hw_mtpr();
749 format HwMoveIPR {
750 1: hw_mtpr({{
751 xc->setMiscRegWithEffect(ipr_index, Ra);
752 if (traceData) { traceData->setData(Ra); }
746 }
747 }
748
749 0x1d: decode PALMODE {
750 0: OpcdecFault::hw_mtpr();
751 format HwMoveIPR {
752 1: hw_mtpr({{
753 xc->setMiscRegWithEffect(ipr_index, Ra);
754 if (traceData) { traceData->setData(Ra); }
753 }}, IsIprAccess);
755 }});
754 }
755 }
756
757 format BasicOperate {
758 0x1e: decode PALMODE {
759 0: OpcdecFault::hw_rei();
756 }
757 }
758
759 format BasicOperate {
760 0x1e: decode PALMODE {
761 0: OpcdecFault::hw_rei();
760 1:hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
762 1:hw_rei({{ xc->hwrei(); }}, IsSerializing);
761 }
762
763 // M5 special opcodes use the reserved 0x01 opcode space
764 0x01: decode M5FUNC {
765 0x00: arm({{
766 AlphaPseudo::arm(xc->xcBase());
767 }}, IsNonSpeculative);
768 0x01: quiesce({{
769 AlphaPseudo::quiesce(xc->xcBase());
763 }
764
765 // M5 special opcodes use the reserved 0x01 opcode space
766 0x01: decode M5FUNC {
767 0x00: arm({{
768 AlphaPseudo::arm(xc->xcBase());
769 }}, IsNonSpeculative);
770 0x01: quiesce({{
771 AlphaPseudo::quiesce(xc->xcBase());
770 }}, IsNonSpeculative, IsQuiesce);
772 }}, IsNonSpeculative);
771 0x02: quiesceNs({{
772 AlphaPseudo::quiesceNs(xc->xcBase(), R16);
773 0x02: quiesceNs({{
774 AlphaPseudo::quiesceNs(xc->xcBase(), R16);
773 }}, IsNonSpeculative, IsQuiesce);
775 }}, IsNonSpeculative);
774 0x03: quiesceCycles({{
775 AlphaPseudo::quiesceCycles(xc->xcBase(), R16);
776 0x03: quiesceCycles({{
777 AlphaPseudo::quiesceCycles(xc->xcBase(), R16);
776 }}, IsNonSpeculative, IsQuiesce);
778 }}, IsNonSpeculative);
777 0x04: quiesceTime({{
778 R0 = AlphaPseudo::quiesceTime(xc->xcBase());
779 }}, IsNonSpeculative);
780 0x10: ivlb({{
781 AlphaPseudo::ivlb(xc->xcBase());
782 }}, No_OpClass, IsNonSpeculative);
783 0x11: ivle({{
784 AlphaPseudo::ivle(xc->xcBase());

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780 R0 = AlphaPseudo::quiesceTime(xc->xcBase());
781 }}, IsNonSpeculative);
782 0x10: ivlb({{
783 AlphaPseudo::ivlb(xc->xcBase());
784 }}, No_OpClass, IsNonSpeculative);
785 0x11: ivle({{
786 AlphaPseudo::ivle(xc->xcBase());

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