decoder.isa (10474:799c8ee4ecba) decoder.isa (11150:a8a64cca231b)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2013 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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938 // M5 special opcodes use the reserved 0x01 opcode space
939 0x01: decode M5FUNC {
940 0x00: arm({{
941 PseudoInst::arm(xc->tcBase());
942 }}, IsNonSpeculative);
943 0x01: quiesce({{
944 // Don't sleep if (unmasked) interrupts are pending
945 Interrupts* interrupts =
1// -*- mode:c++ -*-
2
3// Copyright (c) 2013 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 929 unchanged lines hidden (view full) ---

938 // M5 special opcodes use the reserved 0x01 opcode space
939 0x01: decode M5FUNC {
940 0x00: arm({{
941 PseudoInst::arm(xc->tcBase());
942 }}, IsNonSpeculative);
943 0x01: quiesce({{
944 // Don't sleep if (unmasked) interrupts are pending
945 Interrupts* interrupts =
946 xc->tcBase()->getCpuPtr()->getInterruptController();
946 xc->tcBase()->getCpuPtr()->getInterruptController(0);
947 if (interrupts->checkInterrupts(xc->tcBase())) {
948 PseudoInst::quiesceSkip(xc->tcBase());
949 } else {
950 PseudoInst::quiesce(xc->tcBase());
951 }
952 }}, IsNonSpeculative, IsQuiesce);
953 0x02: quiesceNs({{
954 PseudoInst::quiesceNs(xc->tcBase(), R16);

--- 130 unchanged lines hidden --- 		947 if (interrupts->checkInterrupts(xc->tcBase())) {
948 PseudoInst::quiesceSkip(xc->tcBase());
949 } else {
950 PseudoInst::quiesce(xc->tcBase());
951 }
952 }}, IsNonSpeculative, IsQuiesce);
953 0x02: quiesceNs({{
954 PseudoInst::quiesceNs(xc->tcBase(), R16);

--- 130 unchanged lines hidden ---