1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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778 fault = new UnimplementedOpcodeFault;
779 else
780 xc->setMiscReg(miscRegIndex, Ra);
781 if (traceData) { traceData->setData(Ra); }
782 }}, IsIprAccess);
783 }
784 }
785
786 format BasicOperate {
787 0x1e: decode PALMODE {
788 0: OpcdecFault::hw_rei();
789 1:hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
786 0x1e: decode PALMODE {
787 0: OpcdecFault::hw_rei();
788 format BasicOperate {
789 1: hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
790 }
791 }
792
793#endif
794
795 format BasicOperate {
796 // M5 special opcodes use the reserved 0x01 opcode space
797 0x01: decode M5FUNC {
798#if FULL_SYSTEM
799 0x00: arm({{
800 PseudoInst::arm(xc->tcBase());
801 }}, IsNonSpeculative);
802 0x01: quiesce({{
803 PseudoInst::quiesce(xc->tcBase());
804 }}, IsNonSpeculative, IsQuiesce);
805 0x02: quiesceNs({{
806 PseudoInst::quiesceNs(xc->tcBase(), R16);
807 }}, IsNonSpeculative, IsQuiesce);
808 0x03: quiesceCycles({{
809 PseudoInst::quiesceCycles(xc->tcBase(), R16);
810 }}, IsNonSpeculative, IsQuiesce, IsUnverifiable);
811 0x04: quiesceTime({{
812 R0 = PseudoInst::quiesceTime(xc->tcBase());
813 }}, IsNonSpeculative, IsUnverifiable);
814#endif
815 0x07: rpns({{
816 R0 = PseudoInst::rpns(xc->tcBase());
817 }}, IsNonSpeculative, IsUnverifiable);
818 0x10: deprecated_ivlb({{
819 warn_once("Obsolete M5 ivlb instruction encountered.\n");
820 }});
821 0x11: deprecated_ivle({{
822 warn_once("Obsolete M5 ivlb instruction encountered.\n");
823 }});
824 0x20: deprecated_exit ({{
825 warn_once("deprecated M5 exit instruction encountered.\n");
826 PseudoInst::m5exit(xc->tcBase(), 0);
827 }}, No_OpClass, IsNonSpeculative);
828 0x21: m5exit({{
829 PseudoInst::m5exit(xc->tcBase(), R16);
830 }}, No_OpClass, IsNonSpeculative);
831#if FULL_SYSTEM
832 0x31: loadsymbol({{
833 PseudoInst::loadsymbol(xc->tcBase());
834 }}, No_OpClass, IsNonSpeculative);
835 0x30: initparam({{
836 Ra = xc->tcBase()->getCpuPtr()->system->init_param;
837 }});
838#endif
839 0x40: resetstats({{
840 PseudoInst::resetstats(xc->tcBase(), R16, R17);
841 }}, IsNonSpeculative);
842 0x41: dumpstats({{
843 PseudoInst::dumpstats(xc->tcBase(), R16, R17);
844 }}, IsNonSpeculative);
845 0x42: dumpresetstats({{
846 PseudoInst::dumpresetstats(xc->tcBase(), R16, R17);
847 }}, IsNonSpeculative);
848 0x43: m5checkpoint({{
849 PseudoInst::m5checkpoint(xc->tcBase(), R16, R17);
850 }}, IsNonSpeculative);
851#if FULL_SYSTEM
852 0x50: m5readfile({{
853 R0 = PseudoInst::readfile(xc->tcBase(), R16, R17, R18);
854 }}, IsNonSpeculative);
855#endif
856 0x51: m5break({{
857 PseudoInst::debugbreak(xc->tcBase());
858 }}, IsNonSpeculative);
859 0x52: m5switchcpu({{
860 PseudoInst::switchcpu(xc->tcBase());
861 }}, IsNonSpeculative);
862#if FULL_SYSTEM
863 0x53: m5addsymbol({{
864 PseudoInst::addsymbol(xc->tcBase(), R16, R17);
865 }}, IsNonSpeculative);
866#endif
867 0x54: m5panic({{
868 panic("M5 panic instruction called at pc=%#x.", xc->readPC());
869 }}, IsNonSpeculative);
870 0x55: m5reserved1({{
871 warn("M5 reserved opcode ignored");
872 }}, IsNonSpeculative);
873 0x56: m5reserved2({{
874 warn("M5 reserved opcode ignored");

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879 0x58: m5reserved4({{
880 warn("M5 reserved opcode ignored");
881 }}, IsNonSpeculative);
882 0x59: m5reserved5({{
883 warn("M5 reserved opcode ignored");
884 }}, IsNonSpeculative);
885 }
886 }
875#endif
887}