44,49c44,49
< 0x0a: ldbu({{ Ra.uq = Mem.ub; }});
< 0x0c: ldwu({{ Ra.uq = Mem.uw; }});
< 0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }});
< 0x23: ldt({{ Fa = Mem.df; }});
< 0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LLSC);
< 0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LLSC);
---
> 0x0a: ldbu({{ Ra_uq = Mem_ub; }});
> 0x0c: ldwu({{ Ra_uq = Mem_uw; }});
> 0x0b: ldq_u({{ Ra = Mem_uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }});
> 0x23: ldt({{ Fa = Mem_df; }});
> 0x2a: ldl_l({{ Ra_sl = Mem_sl; }}, mem_flags = LLSC);
> 0x2b: ldq_l({{ Ra_uq = Mem_uq; }}, mem_flags = LLSC);
53,54c53,54
< 0x28: ldl({{ Ra.sl = Mem.sl; }});
< 0x29: ldq({{ Ra.uq = Mem.uq; }}, pf_flags = EVICT_NEXT);
---
> 0x28: ldl({{ Ra_sl = Mem_sl; }});
> 0x29: ldq({{ Ra_uq = Mem_uq; }}, pf_flags = EVICT_NEXT);
57c57
< 0x22: lds({{ Fa.uq = s_to_t(Mem.ul); }},
---
> 0x22: lds({{ Fa_uq = s_to_t(Mem_ul); }},
62,68c62,68
< 0x0e: stb({{ Mem.ub = Ra<7:0>; }});
< 0x0d: stw({{ Mem.uw = Ra<15:0>; }});
< 0x2c: stl({{ Mem.ul = Ra<31:0>; }});
< 0x2d: stq({{ Mem.uq = Ra.uq; }});
< 0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }});
< 0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }});
< 0x27: stt({{ Mem.df = Fa; }});
---
> 0x0e: stb({{ Mem_ub = Ra<7:0>; }});
> 0x0d: stw({{ Mem_uw = Ra<15:0>; }});
> 0x2c: stl({{ Mem_ul = Ra<31:0>; }});
> 0x2d: stq({{ Mem_uq = Ra_uq; }});
> 0x0f: stq_u({{ Mem_uq = Ra_uq; }}, {{ EA = (Rb + disp) & ~7; }});
> 0x26: sts({{ Mem_ul = t_to_s(Fa_uq); }});
> 0x27: stt({{ Mem_df = Fa; }});
72c72
< 0x2e: stl_c({{ Mem.ul = Ra<31:0>; }},
---
> 0x2e: stl_c({{ Mem_ul = Ra<31:0>; }},
81c81
< 0x2f: stq_c({{ Mem.uq = Ra; }},
---
> 0x2f: stq_c({{ Mem_uq = Ra; }},
105c105
< 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
---
> 0x00: addl({{ Rc_sl = Ra_sl + Rb_or_imm_sl; }});
107c107
< int32_t tmp = Ra.sl + Rb_or_imm.sl;
---
> int32_t tmp = Ra_sl + Rb_or_imm_sl;
110c110
< if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
---
> if (Ra_sl<31:> == Rb_or_imm_sl<31:> && tmp<31:> != Ra_sl<31:>)
112c112
< Rc.sl = tmp;
---
> Rc_sl = tmp;
114,115c114,115
< 0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
< 0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }});
---
> 0x02: s4addl({{ Rc_sl = (Ra_sl << 2) + Rb_or_imm_sl; }});
> 0x12: s8addl({{ Rc_sl = (Ra_sl << 3) + Rb_or_imm_sl; }});
129c129
< 0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }});
---
> 0x09: subl({{ Rc_sl = Ra_sl - Rb_or_imm_sl; }});
131c131
< int32_t tmp = Ra.sl - Rb_or_imm.sl;
---
> int32_t tmp = Ra_sl - Rb_or_imm_sl;
136c136
< if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
---
> if (Ra_sl<31:> != Rb_or_imm_sl<31:> && tmp<31:> != Ra_sl<31:>)
138c138
< Rc.sl = tmp;
---
> Rc_sl = tmp;
140,141c140,141
< 0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
< 0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }});
---
> 0x0b: s4subl({{ Rc_sl = (Ra_sl << 2) - Rb_or_imm_sl; }});
> 0x1b: s8subl({{ Rc_sl = (Ra_sl << 3) - Rb_or_imm_sl; }});
158,161c158,161
< 0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }});
< 0x4d: cmplt({{ Rc = (Ra.sq < Rb_or_imm.sq); }});
< 0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }});
< 0x1d: cmpult({{ Rc = (Ra.uq < Rb_or_imm.uq); }});
---
> 0x6d: cmple({{ Rc = (Ra_sq <= Rb_or_imm_sq); }});
> 0x4d: cmplt({{ Rc = (Ra_sq < Rb_or_imm_sq); }});
> 0x3d: cmpule({{ Rc = (Ra_uq <= Rb_or_imm_uq); }});
> 0x1d: cmpult({{ Rc = (Ra_uq < Rb_or_imm_uq); }});
168c168
< tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i;
---
> tmp |= (Ra_uq<hi:lo> >= Rb_or_imm_uq<hi:lo>) << i;
190,193c190,193
< 0x44: cmovlt({{ Rc = (Ra.sq < 0) ? Rb_or_imm : Rc; }});
< 0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }});
< 0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }});
< 0x66: cmovgt({{ Rc = (Ra.sq > 0) ? Rb_or_imm : Rc; }});
---
> 0x44: cmovlt({{ Rc = (Ra_sq < 0) ? Rb_or_imm : Rc; }});
> 0x46: cmovge({{ Rc = (Ra_sq >= 0) ? Rb_or_imm : Rc; }});
> 0x64: cmovle({{ Rc = (Ra_sq <= 0) ? Rb_or_imm : Rc; }});
> 0x66: cmovgt({{ Rc = (Ra_sq > 0) ? Rb_or_imm : Rc; }});
217,218c217,218
< 0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }});
< 0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }});
---
> 0x34: srl({{ Rc = Ra_uq >> Rb_or_imm<5:0>; }});
> 0x3c: sra({{ Rc = Ra_sq >> Rb_or_imm<5:0>; }});
238,241c238,241
< 0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
< 0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
< 0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
< 0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }});
---
> 0x06: extbl({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
> 0x16: extwl({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
> 0x26: extll({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
> 0x36: extql({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8)); }});
257c257
< Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0;
---
> Rc = bv ? (Ra_uq<15:0> >> (64 - 8 * bv)) : 0;
261c261
< Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0;
---
> Rc = bv ? (Ra_uq<31:0> >> (64 - 8 * bv)) : 0;
265c265
< Rc = bv ? (Ra.uq >> (64 - 8 * bv)) : 0;
---
> Rc = bv ? (Ra_uq >> (64 - 8 * bv)) : 0;
287c287
< 0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp);
---
> 0x00: mull({{ Rc_sl = Ra_sl * Rb_or_imm_sl; }}, IntMultOp);
296,297c296,297
< int64_t Rax = Ra.sl; // sign extended version of Ra.sl
< int64_t Rbx = Rb_or_imm.sl;
---
> int64_t Rax = Ra_sl; // sign extended version of Ra_sl
> int64_t Rbx = Rb_or_imm_sl;
305c305
< Rc.sl = tmp<31:0>;
---
> Rc_sl = tmp<31:0>;
321,322c321,322
< 0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
< 0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
---
> 0x00: decode RA { 31: sextb({{ Rc_sb = Rb_or_imm< 7:0>; }}); }
> 0x01: decode RA { 31: sextw({{ Rc_sw = Rb_or_imm<15:0>; }}); }
338,339c338,339
< uint8_t ra_ub = Ra.uq<hi:lo>;
< uint8_t rb_ub = Rb.uq<hi:lo>;
---
> uint8_t ra_ub = Ra_uq<hi:lo>;
> uint8_t rb_ub = Rb_uq<hi:lo>;
378,381c378,381
< Rc = (Rb.uq<7:0>
< | (Rb.uq<15:8> << 16)
< | (Rb.uq<23:16> << 32)
< | (Rb.uq<31:24> << 48));
---
> Rc = (Rb_uq<7:0>
> | (Rb_uq<15:8> << 16)
> | (Rb_uq<23:16> << 32)
> | (Rb_uq<31:24> << 48));
385c385
< Rc = (Rb.uq<7:0> | (Rb.uq<15:8> << 32));
---
> Rc = (Rb_uq<7:0> | (Rb_uq<15:8> << 32));
389,392c389,392
< Rc = (Rb.uq<7:0>
< | (Rb.uq<23:16> << 8)
< | (Rb.uq<39:32> << 16)
< | (Rb.uq<55:48> << 24));
---
> Rc = (Rb_uq<7:0>
> | (Rb_uq<23:16> << 8)
> | (Rb_uq<39:32> << 16)
> | (Rb_uq<55:48> << 24));
396c396
< Rc = (Rb.uq<7:0> | (Rb.uq<39:32> << 8));
---
> Rc = (Rb_uq<7:0> | (Rb_uq<39:32> << 8));
404,405c404,405
< int8_t ra_sb = Ra.uq<hi:lo>;
< int8_t rb_sb = Rb.uq<hi:lo>;
---
> int8_t ra_sb = Ra_uq<hi:lo>;
> int8_t rb_sb = Rb_uq<hi:lo>;
407,408c407,408
< | ((ra_sb < rb_sb) ? Ra.uq<hi:lo>
< : Rb.uq<hi:lo>));
---
> | ((ra_sb < rb_sb) ? Ra_uq<hi:lo>
> : Rb_uq<hi:lo>));
420,421c420,421
< int16_t ra_sw = Ra.uq<hi:lo>;
< int16_t rb_sw = Rb.uq<hi:lo>;
---
> int16_t ra_sw = Ra_uq<hi:lo>;
> int16_t rb_sw = Rb_uq<hi:lo>;
423,424c423,424
< | ((ra_sw < rb_sw) ? Ra.uq<hi:lo>
< : Rb.uq<hi:lo>));
---
> | ((ra_sw < rb_sw) ? Ra_uq<hi:lo>
> : Rb_uq<hi:lo>));
436,437c436,437
< uint8_t ra_ub = Ra.uq<hi:lo>;
< uint8_t rb_ub = Rb.uq<hi:lo>;
---
> uint8_t ra_ub = Ra_uq<hi:lo>;
> uint8_t rb_ub = Rb_uq<hi:lo>;
439,440c439,440
< | ((ra_ub < rb_ub) ? Ra.uq<hi:lo>
< : Rb.uq<hi:lo>));
---
> | ((ra_ub < rb_ub) ? Ra_uq<hi:lo>
> : Rb_uq<hi:lo>));
452,453c452,453
< uint16_t ra_sw = Ra.uq<hi:lo>;
< uint16_t rb_sw = Rb.uq<hi:lo>;
---
> uint16_t ra_sw = Ra_uq<hi:lo>;
> uint16_t rb_sw = Rb_uq<hi:lo>;
455,456c455,456
< | ((ra_sw < rb_sw) ? Ra.uq<hi:lo>
< : Rb.uq<hi:lo>));
---
> | ((ra_sw < rb_sw) ? Ra_uq<hi:lo>
> : Rb_uq<hi:lo>));
468,469c468,469
< uint8_t ra_ub = Ra.uq<hi:lo>;
< uint8_t rb_ub = Rb.uq<hi:lo>;
---
> uint8_t ra_ub = Ra_uq<hi:lo>;
> uint8_t rb_ub = Rb_uq<hi:lo>;
471,472c471,472
< | ((ra_ub > rb_ub) ? Ra.uq<hi:lo>
< : Rb.uq<hi:lo>));
---
> | ((ra_ub > rb_ub) ? Ra_uq<hi:lo>
> : Rb_uq<hi:lo>));
484,485c484,485
< uint16_t ra_uw = Ra.uq<hi:lo>;
< uint16_t rb_uw = Rb.uq<hi:lo>;
---
> uint16_t ra_uw = Ra_uq<hi:lo>;
> uint16_t rb_uw = Rb_uq<hi:lo>;
487,488c487,488
< | ((ra_uw > rb_uw) ? Ra.uq<hi:lo>
< : Rb.uq<hi:lo>));
---
> | ((ra_uw > rb_uw) ? Ra_uq<hi:lo>
> : Rb_uq<hi:lo>));
500,501c500,501
< int8_t ra_sb = Ra.uq<hi:lo>;
< int8_t rb_sb = Rb.uq<hi:lo>;
---
> int8_t ra_sb = Ra_uq<hi:lo>;
> int8_t rb_sb = Rb_uq<hi:lo>;
503,504c503,504
< | ((ra_sb > rb_sb) ? Ra.uq<hi:lo>
< : Rb.uq<hi:lo>));
---
> | ((ra_sb > rb_sb) ? Ra_uq<hi:lo>
> : Rb_uq<hi:lo>));
516,517c516,517
< int16_t ra_sw = Ra.uq<hi:lo>;
< int16_t rb_sw = Rb.uq<hi:lo>;
---
> int16_t ra_sw = Ra_uq<hi:lo>;
> int16_t rb_sw = Rb_uq<hi:lo>;
519,520c519,520
< | ((ra_sw > rb_sw) ? Ra.uq<hi:lo>
< : Rb.uq<hi:lo>));
---
> | ((ra_sw > rb_sw) ? Ra_uq<hi:lo>
> : Rb_uq<hi:lo>));
529c529
< 31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp);
---
> 31: ftoit({{ Rc = Fa_uq; }}, FloatCvtOp);
532c532
< 31: ftois({{ Rc.sl = t_to_s(Fa.uq); }},
---
> 31: ftois({{ Rc_sl = t_to_s(Fa_uq); }},
543,546c543,546
< 0x3e: bge({{ cond = (Ra.sq >= 0); }});
< 0x3f: bgt({{ cond = (Ra.sq > 0); }});
< 0x3b: ble({{ cond = (Ra.sq <= 0); }});
< 0x3a: blt({{ cond = (Ra.sq < 0); }});
---
> 0x3e: bge({{ cond = (Ra_sq >= 0); }});
> 0x3f: bgt({{ cond = (Ra_sq > 0); }});
> 0x3b: ble({{ cond = (Ra_sq <= 0); }});
> 0x3a: blt({{ cond = (Ra_sq < 0); }});
580,581c580,581
< 0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp);
< 0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp);
---
> 0x004: itofs({{ Fc_uq = s_to_t(Ra_ul); }}, FloatCvtOp);
> 0x024: itoft({{ Fc_uq = Ra_uq; }}, FloatCvtOp);
599c599
< if (Fb.sf < 0.0)
---
> if (Fb_sf < 0.0)
601c601
< Fc.sf = sqrt(Fb.sf);
---
> Fc_sf = sqrt(Fb_sf);
641,644c641,644
< 0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }});
< 0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }});
< 0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp);
< 0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp);
---
> 0x00: adds({{ Fc_sf = Fa_sf + Fb_sf; }});
> 0x01: subs({{ Fc_sf = Fa_sf - Fb_sf; }});
> 0x02: muls({{ Fc_sf = Fa_sf * Fb_sf; }}, FloatMultOp);
> 0x03: divs({{ Fc_sf = Fa_sf / Fb_sf; }}, FloatDivOp);
684c684
< 0: cvttq({{ Fc.sq = (int64_t)trunc(Fb); }},
---
> 0: cvttq({{ Fc_sq = (int64_t)trunc(Fb); }},
687c687
< 1: cvttq({{ Fc.sq = (int64_t)floor(Fb); }},
---
> 1: cvttq({{ Fc_sq = (int64_t)floor(Fb); }},
690c690
< default: cvttq({{ Fc.sq = (int64_t)nearbyint(Fb); }});
---
> default: cvttq({{ Fc_sq = (int64_t)nearbyint(Fb); }});
699c699
< 0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }});
---
> 0x2ac, 0x6ac: cvtst({{ Fc = Fb_sf; }});
701c701
< default: cvtts({{ Fc.sf = Fb; }});
---
> default: cvtts({{ Fc_sf = Fb; }});
709c709
< 0,7: cvtqs({{ Fc.sf = Fb.sq; }});
---
> 0,7: cvtqs({{ Fc_sf = Fb_sq; }});
712c712
< 0,7: cvtqt({{ Fc = Fb.sq; }});
---
> 0,7: cvtqt({{ Fc = Fb_sq; }});
723c723
< Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>;
---
> Fc_sl = (Fb_uq<63:62> << 30) | Fb_uq<58:29>;
726c726
< Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
---
> Fc_uq = (Fb_uq<31:30> << 62) | (Fb_uq<29:0> << 29);
735c735
< uint64_t sign_bits = Fb.uq<63:31>;
---
> uint64_t sign_bits = Fb_uq<63:31>;
738c738
< Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
---
> Fc_uq = (Fb_uq<31:30> << 62) | (Fb_uq<29:0> << 29);
742c742
< Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>;
---
> Fc_uq = (Fa_uq<63:> << 63) | Fb_uq<62:0>;
745c745
< Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>;
---
> Fc_uq = (~Fa_uq<63:> << 63) | Fb_uq<62:0>;
748c748
< Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>;
---
> Fc_uq = (Fa_uq<63:52> << 52) | Fb_uq<51:0>;
758,759c758,759
< 0x024: mt_fpcr({{ FPCR = Fa.uq; }}, IsIprAccess);
< 0x025: mf_fpcr({{ Fa.uq = FPCR; }}, IsIprAccess);
---
> 0x024: mt_fpcr({{ FPCR = Fa_uq; }}, IsIprAccess);
> 0x025: mf_fpcr({{ Fa_uq = FPCR; }}, IsIprAccess);
865c865
< 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }},
---
> 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem_ul; }},
867c867
< 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }},
---
> 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem_uq; }},
879c879
< {{ Mem.ul = Ra<31:0>; }}, L, IsSerializing, IsSerializeBefore);
---
> {{ Mem_ul = Ra<31:0>; }}, L, IsSerializing, IsSerializeBefore);
881c881
< {{ Mem.uq = Ra.uq; }}, Q, IsSerializing, IsSerializeBefore);
---
> {{ Mem_uq = Ra_uq; }}, Q, IsSerializing, IsSerializeBefore);
< 0x0a: ldbu({{ Ra.uq = Mem.ub; }});
< 0x0c: ldwu({{ Ra.uq = Mem.uw; }});
< 0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }});
< 0x23: ldt({{ Fa = Mem.df; }});
< 0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LLSC);
< 0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LLSC);
---
> 0x0a: ldbu({{ Ra_uq = Mem_ub; }});
> 0x0c: ldwu({{ Ra_uq = Mem_uw; }});
> 0x0b: ldq_u({{ Ra = Mem_uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }});
> 0x23: ldt({{ Fa = Mem_df; }});
> 0x2a: ldl_l({{ Ra_sl = Mem_sl; }}, mem_flags = LLSC);
> 0x2b: ldq_l({{ Ra_uq = Mem_uq; }}, mem_flags = LLSC);
53,54c53,54
< 0x28: ldl({{ Ra.sl = Mem.sl; }});
< 0x29: ldq({{ Ra.uq = Mem.uq; }}, pf_flags = EVICT_NEXT);
---
> 0x28: ldl({{ Ra_sl = Mem_sl; }});
> 0x29: ldq({{ Ra_uq = Mem_uq; }}, pf_flags = EVICT_NEXT);
57c57
< 0x22: lds({{ Fa.uq = s_to_t(Mem.ul); }},
---
> 0x22: lds({{ Fa_uq = s_to_t(Mem_ul); }},
62,68c62,68
< 0x0e: stb({{ Mem.ub = Ra<7:0>; }});
< 0x0d: stw({{ Mem.uw = Ra<15:0>; }});
< 0x2c: stl({{ Mem.ul = Ra<31:0>; }});
< 0x2d: stq({{ Mem.uq = Ra.uq; }});
< 0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }});
< 0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }});
< 0x27: stt({{ Mem.df = Fa; }});
---
> 0x0e: stb({{ Mem_ub = Ra<7:0>; }});
> 0x0d: stw({{ Mem_uw = Ra<15:0>; }});
> 0x2c: stl({{ Mem_ul = Ra<31:0>; }});
> 0x2d: stq({{ Mem_uq = Ra_uq; }});
> 0x0f: stq_u({{ Mem_uq = Ra_uq; }}, {{ EA = (Rb + disp) & ~7; }});
> 0x26: sts({{ Mem_ul = t_to_s(Fa_uq); }});
> 0x27: stt({{ Mem_df = Fa; }});
72c72
< 0x2e: stl_c({{ Mem.ul = Ra<31:0>; }},
---
> 0x2e: stl_c({{ Mem_ul = Ra<31:0>; }},
81c81
< 0x2f: stq_c({{ Mem.uq = Ra; }},
---
> 0x2f: stq_c({{ Mem_uq = Ra; }},
105c105
< 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
---
> 0x00: addl({{ Rc_sl = Ra_sl + Rb_or_imm_sl; }});
107c107
< int32_t tmp = Ra.sl + Rb_or_imm.sl;
---
> int32_t tmp = Ra_sl + Rb_or_imm_sl;
110c110
< if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
---
> if (Ra_sl<31:> == Rb_or_imm_sl<31:> && tmp<31:> != Ra_sl<31:>)
112c112
< Rc.sl = tmp;
---
> Rc_sl = tmp;
114,115c114,115
< 0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
< 0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }});
---
> 0x02: s4addl({{ Rc_sl = (Ra_sl << 2) + Rb_or_imm_sl; }});
> 0x12: s8addl({{ Rc_sl = (Ra_sl << 3) + Rb_or_imm_sl; }});
129c129
< 0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }});
---
> 0x09: subl({{ Rc_sl = Ra_sl - Rb_or_imm_sl; }});
131c131
< int32_t tmp = Ra.sl - Rb_or_imm.sl;
---
> int32_t tmp = Ra_sl - Rb_or_imm_sl;
136c136
< if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
---
> if (Ra_sl<31:> != Rb_or_imm_sl<31:> && tmp<31:> != Ra_sl<31:>)
138c138
< Rc.sl = tmp;
---
> Rc_sl = tmp;
140,141c140,141
< 0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
< 0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }});
---
> 0x0b: s4subl({{ Rc_sl = (Ra_sl << 2) - Rb_or_imm_sl; }});
> 0x1b: s8subl({{ Rc_sl = (Ra_sl << 3) - Rb_or_imm_sl; }});
158,161c158,161
< 0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }});
< 0x4d: cmplt({{ Rc = (Ra.sq < Rb_or_imm.sq); }});
< 0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }});
< 0x1d: cmpult({{ Rc = (Ra.uq < Rb_or_imm.uq); }});
---
> 0x6d: cmple({{ Rc = (Ra_sq <= Rb_or_imm_sq); }});
> 0x4d: cmplt({{ Rc = (Ra_sq < Rb_or_imm_sq); }});
> 0x3d: cmpule({{ Rc = (Ra_uq <= Rb_or_imm_uq); }});
> 0x1d: cmpult({{ Rc = (Ra_uq < Rb_or_imm_uq); }});
168c168
< tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i;
---
> tmp |= (Ra_uq<hi:lo> >= Rb_or_imm_uq<hi:lo>) << i;
190,193c190,193
< 0x44: cmovlt({{ Rc = (Ra.sq < 0) ? Rb_or_imm : Rc; }});
< 0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }});
< 0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }});
< 0x66: cmovgt({{ Rc = (Ra.sq > 0) ? Rb_or_imm : Rc; }});
---
> 0x44: cmovlt({{ Rc = (Ra_sq < 0) ? Rb_or_imm : Rc; }});
> 0x46: cmovge({{ Rc = (Ra_sq >= 0) ? Rb_or_imm : Rc; }});
> 0x64: cmovle({{ Rc = (Ra_sq <= 0) ? Rb_or_imm : Rc; }});
> 0x66: cmovgt({{ Rc = (Ra_sq > 0) ? Rb_or_imm : Rc; }});
217,218c217,218
< 0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }});
< 0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }});
---
> 0x34: srl({{ Rc = Ra_uq >> Rb_or_imm<5:0>; }});
> 0x3c: sra({{ Rc = Ra_sq >> Rb_or_imm<5:0>; }});
238,241c238,241
< 0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
< 0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
< 0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
< 0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }});
---
> 0x06: extbl({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
> 0x16: extwl({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
> 0x26: extll({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
> 0x36: extql({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8)); }});
257c257
< Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0;
---
> Rc = bv ? (Ra_uq<15:0> >> (64 - 8 * bv)) : 0;
261c261
< Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0;
---
> Rc = bv ? (Ra_uq<31:0> >> (64 - 8 * bv)) : 0;
265c265
< Rc = bv ? (Ra.uq >> (64 - 8 * bv)) : 0;
---
> Rc = bv ? (Ra_uq >> (64 - 8 * bv)) : 0;
287c287
< 0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp);
---
> 0x00: mull({{ Rc_sl = Ra_sl * Rb_or_imm_sl; }}, IntMultOp);
296,297c296,297
< int64_t Rax = Ra.sl; // sign extended version of Ra.sl
< int64_t Rbx = Rb_or_imm.sl;
---
> int64_t Rax = Ra_sl; // sign extended version of Ra_sl
> int64_t Rbx = Rb_or_imm_sl;
305c305
< Rc.sl = tmp<31:0>;
---
> Rc_sl = tmp<31:0>;
321,322c321,322
< 0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
< 0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
---
> 0x00: decode RA { 31: sextb({{ Rc_sb = Rb_or_imm< 7:0>; }}); }
> 0x01: decode RA { 31: sextw({{ Rc_sw = Rb_or_imm<15:0>; }}); }
338,339c338,339
< uint8_t ra_ub = Ra.uq<hi:lo>;
< uint8_t rb_ub = Rb.uq<hi:lo>;
---
> uint8_t ra_ub = Ra_uq<hi:lo>;
> uint8_t rb_ub = Rb_uq<hi:lo>;
378,381c378,381
< Rc = (Rb.uq<7:0>
< | (Rb.uq<15:8> << 16)
< | (Rb.uq<23:16> << 32)
< | (Rb.uq<31:24> << 48));
---
> Rc = (Rb_uq<7:0>
> | (Rb_uq<15:8> << 16)
> | (Rb_uq<23:16> << 32)
> | (Rb_uq<31:24> << 48));
385c385
< Rc = (Rb.uq<7:0> | (Rb.uq<15:8> << 32));
---
> Rc = (Rb_uq<7:0> | (Rb_uq<15:8> << 32));
389,392c389,392
< Rc = (Rb.uq<7:0>
< | (Rb.uq<23:16> << 8)
< | (Rb.uq<39:32> << 16)
< | (Rb.uq<55:48> << 24));
---
> Rc = (Rb_uq<7:0>
> | (Rb_uq<23:16> << 8)
> | (Rb_uq<39:32> << 16)
> | (Rb_uq<55:48> << 24));
396c396
< Rc = (Rb.uq<7:0> | (Rb.uq<39:32> << 8));
---
> Rc = (Rb_uq<7:0> | (Rb_uq<39:32> << 8));
404,405c404,405
< int8_t ra_sb = Ra.uq<hi:lo>;
< int8_t rb_sb = Rb.uq<hi:lo>;
---
> int8_t ra_sb = Ra_uq<hi:lo>;
> int8_t rb_sb = Rb_uq<hi:lo>;
407,408c407,408
< | ((ra_sb < rb_sb) ? Ra.uq<hi:lo>
< : Rb.uq<hi:lo>));
---
> | ((ra_sb < rb_sb) ? Ra_uq<hi:lo>
> : Rb_uq<hi:lo>));
420,421c420,421
< int16_t ra_sw = Ra.uq<hi:lo>;
< int16_t rb_sw = Rb.uq<hi:lo>;
---
> int16_t ra_sw = Ra_uq<hi:lo>;
> int16_t rb_sw = Rb_uq<hi:lo>;
423,424c423,424
< | ((ra_sw < rb_sw) ? Ra.uq<hi:lo>
< : Rb.uq<hi:lo>));
---
> | ((ra_sw < rb_sw) ? Ra_uq<hi:lo>
> : Rb_uq<hi:lo>));
436,437c436,437
< uint8_t ra_ub = Ra.uq<hi:lo>;
< uint8_t rb_ub = Rb.uq<hi:lo>;
---
> uint8_t ra_ub = Ra_uq<hi:lo>;
> uint8_t rb_ub = Rb_uq<hi:lo>;
439,440c439,440
< | ((ra_ub < rb_ub) ? Ra.uq<hi:lo>
< : Rb.uq<hi:lo>));
---
> | ((ra_ub < rb_ub) ? Ra_uq<hi:lo>
> : Rb_uq<hi:lo>));
452,453c452,453
< uint16_t ra_sw = Ra.uq<hi:lo>;
< uint16_t rb_sw = Rb.uq<hi:lo>;
---
> uint16_t ra_sw = Ra_uq<hi:lo>;
> uint16_t rb_sw = Rb_uq<hi:lo>;
455,456c455,456
< | ((ra_sw < rb_sw) ? Ra.uq<hi:lo>
< : Rb.uq<hi:lo>));
---
> | ((ra_sw < rb_sw) ? Ra_uq<hi:lo>
> : Rb_uq<hi:lo>));
468,469c468,469
< uint8_t ra_ub = Ra.uq<hi:lo>;
< uint8_t rb_ub = Rb.uq<hi:lo>;
---
> uint8_t ra_ub = Ra_uq<hi:lo>;
> uint8_t rb_ub = Rb_uq<hi:lo>;
471,472c471,472
< | ((ra_ub > rb_ub) ? Ra.uq<hi:lo>
< : Rb.uq<hi:lo>));
---
> | ((ra_ub > rb_ub) ? Ra_uq<hi:lo>
> : Rb_uq<hi:lo>));
484,485c484,485
< uint16_t ra_uw = Ra.uq<hi:lo>;
< uint16_t rb_uw = Rb.uq<hi:lo>;
---
> uint16_t ra_uw = Ra_uq<hi:lo>;
> uint16_t rb_uw = Rb_uq<hi:lo>;
487,488c487,488
< | ((ra_uw > rb_uw) ? Ra.uq<hi:lo>
< : Rb.uq<hi:lo>));
---
> | ((ra_uw > rb_uw) ? Ra_uq<hi:lo>
> : Rb_uq<hi:lo>));
500,501c500,501
< int8_t ra_sb = Ra.uq<hi:lo>;
< int8_t rb_sb = Rb.uq<hi:lo>;
---
> int8_t ra_sb = Ra_uq<hi:lo>;
> int8_t rb_sb = Rb_uq<hi:lo>;
503,504c503,504
< | ((ra_sb > rb_sb) ? Ra.uq<hi:lo>
< : Rb.uq<hi:lo>));
---
> | ((ra_sb > rb_sb) ? Ra_uq<hi:lo>
> : Rb_uq<hi:lo>));
516,517c516,517
< int16_t ra_sw = Ra.uq<hi:lo>;
< int16_t rb_sw = Rb.uq<hi:lo>;
---
> int16_t ra_sw = Ra_uq<hi:lo>;
> int16_t rb_sw = Rb_uq<hi:lo>;
519,520c519,520
< | ((ra_sw > rb_sw) ? Ra.uq<hi:lo>
< : Rb.uq<hi:lo>));
---
> | ((ra_sw > rb_sw) ? Ra_uq<hi:lo>
> : Rb_uq<hi:lo>));
529c529
< 31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp);
---
> 31: ftoit({{ Rc = Fa_uq; }}, FloatCvtOp);
532c532
< 31: ftois({{ Rc.sl = t_to_s(Fa.uq); }},
---
> 31: ftois({{ Rc_sl = t_to_s(Fa_uq); }},
543,546c543,546
< 0x3e: bge({{ cond = (Ra.sq >= 0); }});
< 0x3f: bgt({{ cond = (Ra.sq > 0); }});
< 0x3b: ble({{ cond = (Ra.sq <= 0); }});
< 0x3a: blt({{ cond = (Ra.sq < 0); }});
---
> 0x3e: bge({{ cond = (Ra_sq >= 0); }});
> 0x3f: bgt({{ cond = (Ra_sq > 0); }});
> 0x3b: ble({{ cond = (Ra_sq <= 0); }});
> 0x3a: blt({{ cond = (Ra_sq < 0); }});
580,581c580,581
< 0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp);
< 0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp);
---
> 0x004: itofs({{ Fc_uq = s_to_t(Ra_ul); }}, FloatCvtOp);
> 0x024: itoft({{ Fc_uq = Ra_uq; }}, FloatCvtOp);
599c599
< if (Fb.sf < 0.0)
---
> if (Fb_sf < 0.0)
601c601
< Fc.sf = sqrt(Fb.sf);
---
> Fc_sf = sqrt(Fb_sf);
641,644c641,644
< 0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }});
< 0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }});
< 0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp);
< 0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp);
---
> 0x00: adds({{ Fc_sf = Fa_sf + Fb_sf; }});
> 0x01: subs({{ Fc_sf = Fa_sf - Fb_sf; }});
> 0x02: muls({{ Fc_sf = Fa_sf * Fb_sf; }}, FloatMultOp);
> 0x03: divs({{ Fc_sf = Fa_sf / Fb_sf; }}, FloatDivOp);
684c684
< 0: cvttq({{ Fc.sq = (int64_t)trunc(Fb); }},
---
> 0: cvttq({{ Fc_sq = (int64_t)trunc(Fb); }},
687c687
< 1: cvttq({{ Fc.sq = (int64_t)floor(Fb); }},
---
> 1: cvttq({{ Fc_sq = (int64_t)floor(Fb); }},
690c690
< default: cvttq({{ Fc.sq = (int64_t)nearbyint(Fb); }});
---
> default: cvttq({{ Fc_sq = (int64_t)nearbyint(Fb); }});
699c699
< 0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }});
---
> 0x2ac, 0x6ac: cvtst({{ Fc = Fb_sf; }});
701c701
< default: cvtts({{ Fc.sf = Fb; }});
---
> default: cvtts({{ Fc_sf = Fb; }});
709c709
< 0,7: cvtqs({{ Fc.sf = Fb.sq; }});
---
> 0,7: cvtqs({{ Fc_sf = Fb_sq; }});
712c712
< 0,7: cvtqt({{ Fc = Fb.sq; }});
---
> 0,7: cvtqt({{ Fc = Fb_sq; }});
723c723
< Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>;
---
> Fc_sl = (Fb_uq<63:62> << 30) | Fb_uq<58:29>;
726c726
< Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
---
> Fc_uq = (Fb_uq<31:30> << 62) | (Fb_uq<29:0> << 29);
735c735
< uint64_t sign_bits = Fb.uq<63:31>;
---
> uint64_t sign_bits = Fb_uq<63:31>;
738c738
< Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
---
> Fc_uq = (Fb_uq<31:30> << 62) | (Fb_uq<29:0> << 29);
742c742
< Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>;
---
> Fc_uq = (Fa_uq<63:> << 63) | Fb_uq<62:0>;
745c745
< Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>;
---
> Fc_uq = (~Fa_uq<63:> << 63) | Fb_uq<62:0>;
748c748
< Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>;
---
> Fc_uq = (Fa_uq<63:52> << 52) | Fb_uq<51:0>;
758,759c758,759
< 0x024: mt_fpcr({{ FPCR = Fa.uq; }}, IsIprAccess);
< 0x025: mf_fpcr({{ Fa.uq = FPCR; }}, IsIprAccess);
---
> 0x024: mt_fpcr({{ FPCR = Fa_uq; }}, IsIprAccess);
> 0x025: mf_fpcr({{ Fa_uq = FPCR; }}, IsIprAccess);
865c865
< 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }},
---
> 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem_ul; }},
867c867
< 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }},
---
> 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem_uq; }},
879c879
< {{ Mem.ul = Ra<31:0>; }}, L, IsSerializing, IsSerializeBefore);
---
> {{ Mem_ul = Ra<31:0>; }}, L, IsSerializing, IsSerializeBefore);
881c881
< {{ Mem.uq = Ra.uq; }}, Q, IsSerializing, IsSerializeBefore);
---
> {{ Mem_uq = Ra_uq; }}, Q, IsSerializing, IsSerializeBefore);