1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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816 0: FailUnimpl::rs_se();
817 default: BasicOperate::rs({{
818 Ra = IntrFlag;
819 IntrFlag = 1;
820 }}, IsNonSpeculative, IsUnverifiable);
821 }
822 }
823
824#if FULL_SYSTEM
825 0x00: CallPal::call_pal({{
826 if (!palValid ||
827 (palPriv
828 && xc->readMiscReg(IPR_ICM) != mode_kernel)) {
829 // invalid pal function code, or attempt to do privileged
830 // PAL call in non-kernel mode
831 fault = new UnimplementedOpcodeFault;
832 } else {
833 // check to see if simulator wants to do something special
834 // on this PAL call (including maybe suppress it)
835 bool dopal = xc->simPalCheck(palFunc);
836
837 if (dopal) {
838 xc->setMiscReg(IPR_EXC_ADDR, NPC);
839 NPC = xc->readMiscReg(IPR_PAL_BASE) + palOffset;
840 }
841 }
842 }}, IsNonSpeculative);
843#else
844 0x00: decode PALFUNC {
845 format EmulatedCallPal {
846 0x00: halt ({{
847 exitSimLoop("halt instruction encountered");
848 }}, IsNonSpeculative);
849 0x83: callsys({{
850 xc->syscall(R0);
851 }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
852 // Read uniq reg into ABI return value register (r0)
853 0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
854 // Write uniq reg with value from ABI arg register (r16)
855 0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess);
856 }
857 }
858#endif
859
860#if FULL_SYSTEM
861 0x1b: decode PALMODE {
862 0: OpcdecFault::hw_st_quad();
863 1: decode HW_LDST_QUAD {
864 format HwLoad {
865 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem_ul; }},
866 L, IsSerializing, IsSerializeBefore);
867 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem_uq; }},
868 Q, IsSerializing, IsSerializeBefore);

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919
920 0x1e: decode PALMODE {
921 0: OpcdecFault::hw_rei();
922 format BasicOperate {
923 1: hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
924 }
925 }
926
927#endif
928
929 format BasicOperate {
930 // M5 special opcodes use the reserved 0x01 opcode space
931 0x01: decode M5FUNC {
932 0x00: arm({{
933 PseudoInst::arm(xc->tcBase());
934 }}, IsNonSpeculative);
935 0x01: quiesce({{
936 PseudoInst::quiesce(xc->tcBase());

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