1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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778 fault = new UnimplementedOpcodeFault;
779 else
780 xc->setMiscReg(miscRegIndex, Ra);
781 if (traceData) { traceData->setData(Ra); }
782 }}, IsIprAccess);
783 }
784 }
785
786 format BasicOperate {
787 0x1e: decode PALMODE {
788 0: OpcdecFault::hw_rei();
789 1:hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
790 }
791
792 // M5 special opcodes use the reserved 0x01 opcode space
793 0x01: decode M5FUNC {
794 0x00: arm({{
795 PseudoInst::arm(xc->tcBase());
796 }}, IsNonSpeculative);
797 0x01: quiesce({{
798 PseudoInst::quiesce(xc->tcBase());
799 }}, IsNonSpeculative, IsQuiesce);
800 0x02: quiesceNs({{
801 PseudoInst::quiesceNs(xc->tcBase(), R16);
802 }}, IsNonSpeculative, IsQuiesce);
803 0x03: quiesceCycles({{
804 PseudoInst::quiesceCycles(xc->tcBase(), R16);
805 }}, IsNonSpeculative, IsQuiesce, IsUnverifiable);
806 0x04: quiesceTime({{
807 R0 = PseudoInst::quiesceTime(xc->tcBase());
808 }}, IsNonSpeculative, IsUnverifiable);
809 0x07: rpns({{
810 R0 = PseudoInst::rpns(xc->tcBase());
811 }}, IsNonSpeculative, IsUnverifiable);
812 0x10: deprecated_ivlb({{
813 warn_once("Obsolete M5 ivlb instruction encountered.\n");
814 }});
815 0x11: deprecated_ivle({{
816 warn_once("Obsolete M5 ivlb instruction encountered.\n");
817 }});
818 0x20: deprecated_exit ({{
819 warn_once("deprecated M5 exit instruction encountered.\n");
820 PseudoInst::m5exit(xc->tcBase(), 0);
821 }}, No_OpClass, IsNonSpeculative);
822 0x21: m5exit({{
823 PseudoInst::m5exit(xc->tcBase(), R16);
824 }}, No_OpClass, IsNonSpeculative);
825 0x31: loadsymbol({{
826 PseudoInst::loadsymbol(xc->tcBase());
827 }}, No_OpClass, IsNonSpeculative);
828 0x30: initparam({{
829 Ra = xc->tcBase()->getCpuPtr()->system->init_param;
830 }});
831 0x40: resetstats({{
832 PseudoInst::resetstats(xc->tcBase(), R16, R17);
833 }}, IsNonSpeculative);
834 0x41: dumpstats({{
835 PseudoInst::dumpstats(xc->tcBase(), R16, R17);
836 }}, IsNonSpeculative);
837 0x42: dumpresetstats({{
838 PseudoInst::dumpresetstats(xc->tcBase(), R16, R17);
839 }}, IsNonSpeculative);
840 0x43: m5checkpoint({{
841 PseudoInst::m5checkpoint(xc->tcBase(), R16, R17);
842 }}, IsNonSpeculative);
843 0x50: m5readfile({{
844 R0 = PseudoInst::readfile(xc->tcBase(), R16, R17, R18);
845 }}, IsNonSpeculative);
846 0x51: m5break({{
847 PseudoInst::debugbreak(xc->tcBase());
848 }}, IsNonSpeculative);
849 0x52: m5switchcpu({{
850 PseudoInst::switchcpu(xc->tcBase());
851 }}, IsNonSpeculative);
852 0x53: m5addsymbol({{
853 PseudoInst::addsymbol(xc->tcBase(), R16, R17);
854 }}, IsNonSpeculative);
855 0x54: m5panic({{
856 panic("M5 panic instruction called at pc=%#x.", xc->readPC());
857 }}, IsNonSpeculative);
858 0x55: m5reserved1({{
859 warn("M5 reserved opcode ignored");
860 }}, IsNonSpeculative);
861 0x56: m5reserved2({{
862 warn("M5 reserved opcode ignored");

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867 0x58: m5reserved4({{
868 warn("M5 reserved opcode ignored");
869 }}, IsNonSpeculative);
870 0x59: m5reserved5({{
871 warn("M5 reserved opcode ignored");
872 }}, IsNonSpeculative);
873 }
874 }
875#endif
876}