1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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801 PseudoInst::quiesceNs(xc->tcBase(), R16);
802 }}, IsNonSpeculative, IsQuiesce);
803 0x03: quiesceCycles({{
804 PseudoInst::quiesceCycles(xc->tcBase(), R16);
805 }}, IsNonSpeculative, IsQuiesce, IsUnverifiable);
806 0x04: quiesceTime({{
807 R0 = PseudoInst::quiesceTime(xc->tcBase());
808 }}, IsNonSpeculative, IsUnverifiable);
809 0x10: ivlb({{
810 warn_once("Obsolete M5 instruction ivlb encountered.\n");
811 }});
812 0x11: ivle({{
813 warn_once("Obsolete M5 instruction ivlb encountered.\n");
814 }});
815 0x20: m5exit_old({{
816 PseudoInst::m5exit_old(xc->tcBase());
817 }}, No_OpClass, IsNonSpeculative);
818 0x21: m5exit({{
819 PseudoInst::m5exit(xc->tcBase(), R16);
820 }}, No_OpClass, IsNonSpeculative);
821 0x31: loadsymbol({{
822 PseudoInst::loadsymbol(xc->tcBase());
823 }}, No_OpClass, IsNonSpeculative);
824 0x30: initparam({{ Ra = xc->tcBase()->getCpuPtr()->system->init_param; }});
825 0x40: resetstats({{
826 PseudoInst::resetstats(xc->tcBase(), R16, R17);
827 }}, IsNonSpeculative);
828 0x41: dumpstats({{
829 PseudoInst::dumpstats(xc->tcBase(), R16, R17);
830 }}, IsNonSpeculative);
831 0x42: dumpresetstats({{
832 PseudoInst::dumpresetstats(xc->tcBase(), R16, R17);

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844 PseudoInst::switchcpu(xc->tcBase());
845 }}, IsNonSpeculative);
846 0x53: m5addsymbol({{
847 PseudoInst::addsymbol(xc->tcBase(), R16, R17);
848 }}, IsNonSpeculative);
849 0x54: m5panic({{
850 panic("M5 panic instruction called at pc=%#x.", xc->readPC());
851 }}, IsNonSpeculative);
852 0x55: m5anBegin({{
853 PseudoInst::anBegin(xc->tcBase(), R16);
854 }}, IsNonSpeculative);
855 0x56: m5anWait({{
856 PseudoInst::anWait(xc->tcBase(), R16, R17);
857 }}, IsNonSpeculative);
858 }
859 }
860#endif
861}