1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28
29////////////////////////////////////////////////////////////////////
30//
31// The actual decoder specification
32//
33
34decode OPCODE default Unknown::unknown() {
35

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73 }
74
75 format StoreCond {
76 0x2e: stl_c({{ Mem.ul = Ra<31:0>; }},
77 {{
78 uint64_t tmp = write_result;
79 // see stq_c
80 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
81 }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
82 0x2f: stq_c({{ Mem.uq = Ra; }},
83 {{
84 uint64_t tmp = write_result;
85 // If the write operation returns 0 or 1, then
86 // this was a conventional store conditional,
87 // and the value indicates the success/failure
88 // of the operation. If another value is
89 // returned, then this was a Turbolaser
90 // mailbox access, and we don't update the
91 // result register at all.
92 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
93 }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
94 }
95
96 format IntegerOperate {
97
98 0x10: decode INTFUNC { // integer arithmetic operations
99
100 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
101 0x40: addlv({{

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591
592 0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
593 0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }});
594 0x02c: fcmovlt({{ Fc = (Fa < 0) ? Fb : Fc; }});
595 0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }});
596 0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
597 0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }});
598
599 0x024: mt_fpcr({{ FPCR = Fa.uq; }}, IsIprAccess);
600 0x025: mf_fpcr({{ Fa.uq = FPCR; }}, IsIprAccess);
601 }
602 }
603
604 // miscellaneous mem-format ops
605 0x18: decode MEMFUNC {
606 format WarnUnimpl {
607 0x8000: fetch();
608 0xa000: fetch_m();

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623 /* Rb is a fake dependency so here is a fun way to get
624 * the parser to understand that.
625 */
626 Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC, fault) + (Rb & 0);
627
628#else
629 Ra = curTick;
630#endif
631 }}, IsUnverifiable);
632
633 // All of the barrier instructions below do nothing in
634 // their execute() methods (hence the empty code blocks).
635 // All of their functionality is hard-coded in the
636 // pipeline based on the flags IsSerializing,
637 // IsMemBarrier, and IsWriteBarrier. In the current
638 // detailed CPU model, the execute() function only gets
639 // called at fetch, so there's no way to generate pipeline
640 // behavior at any other stage. Once we go to an
641 // exec-in-exec CPU model we should be able to get rid of
642 // these flags and implement this behavior via the
643 // execute() methods.
644
645 // trapb is just a barrier on integer traps, where excb is
646 // a barrier on integer and FP traps. "EXCB is thus a
647 // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
648 // them the same though.
649 0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
650 0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
651 0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
652 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
653 }
654
655#if FULL_SYSTEM
656 format BasicOperate {
657 0xe000: rc({{
658 Ra = xc->readIntrFlag();

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696 format EmulatedCallPal {
697 0x00: halt ({{
698 SimExit(curTick, "halt instruction encountered");
699 }}, IsNonSpeculative);
700 0x83: callsys({{
701 xc->syscall(R0);
702 }}, IsNonSpeculative);
703 // Read uniq reg into ABI return value register (r0)
704 0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
705 // Write uniq reg with value from ABI arg register (r16)
706 0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess);
707 }
708 }
709#endif
710
711#if FULL_SYSTEM
712 0x1b: decode PALMODE {
713 0: OpcdecFault::hw_st_quad();
714 1: decode HW_LDST_QUAD {

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735 }
736 }
737
738 0x19: decode PALMODE {
739 0: OpcdecFault::hw_mfpr();
740 format HwMoveIPR {
741 1: hw_mfpr({{
742 Ra = xc->readMiscRegWithEffect(ipr_index, fault);
743 }}, IsIprAccess);
744 }
745 }
746
747 0x1d: decode PALMODE {
748 0: OpcdecFault::hw_mtpr();
749 format HwMoveIPR {
750 1: hw_mtpr({{
751 xc->setMiscRegWithEffect(ipr_index, Ra);
752 if (traceData) { traceData->setData(Ra); }
753 }}, IsIprAccess);
754 }
755 }
756
757 format BasicOperate {
758 0x1e: decode PALMODE {
759 0: OpcdecFault::hw_rei();
760 1:hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
761 }
762
763 // M5 special opcodes use the reserved 0x01 opcode space
764 0x01: decode M5FUNC {
765 0x00: arm({{
766 AlphaPseudo::arm(xc->xcBase());
767 }}, IsNonSpeculative);
768 0x01: quiesce({{
769 AlphaPseudo::quiesce(xc->xcBase());
770 }}, IsNonSpeculative, IsQuiesce);
771 0x02: quiesceNs({{
772 AlphaPseudo::quiesceNs(xc->xcBase(), R16);
773 }}, IsNonSpeculative, IsQuiesce);
774 0x03: quiesceCycles({{
775 AlphaPseudo::quiesceCycles(xc->xcBase(), R16);
776 }}, IsNonSpeculative, IsQuiesce);
777 0x04: quiesceTime({{
778 R0 = AlphaPseudo::quiesceTime(xc->xcBase());
779 }}, IsNonSpeculative);
780 0x10: ivlb({{
781 AlphaPseudo::ivlb(xc->xcBase());
782 }}, No_OpClass, IsNonSpeculative);
783 0x11: ivle({{
784 AlphaPseudo::ivle(xc->xcBase());

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