1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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816 0: FailUnimpl::rs_se();
817 default: BasicOperate::rs({{
818 Ra = IntrFlag;
819 IntrFlag = 1;
820 }}, IsNonSpeculative, IsUnverifiable);
821 }
822 }
823
824 0x00: decode FullSystem {
825 0: decode PALFUNC {
826 format EmulatedCallPal {
827 0x00: halt ({{
828 exitSimLoop("halt instruction encountered");
829 }}, IsNonSpeculative);
830 0x83: callsys({{
831 xc->syscall(R0);
832 }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
833 // Read uniq reg into ABI return value register (r0)
834 0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
835 // Write uniq reg with value from ABI arg register (r16)
836 0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess);
837 }
838 }
839 default: CallPal::call_pal({{
840 if (!palValid ||
841 (palPriv
842 && xc->readMiscReg(IPR_ICM) != mode_kernel)) {
843 // invalid pal function code, or attempt to do privileged
844 // PAL call in non-kernel mode
845 fault = new UnimplementedOpcodeFault;
846 } else {
847 // check to see if simulator wants to do something special
848 // on this PAL call (including maybe suppress it)
849 bool dopal = xc->simPalCheck(palFunc);
850
851 if (dopal) {
852 xc->setMiscReg(IPR_EXC_ADDR, NPC);
853 NPC = xc->readMiscReg(IPR_PAL_BASE) + palOffset;
854 }
855 }
856 }}, IsNonSpeculative);
857 }
858
859 0x1b: decode PALMODE {
860 0: OpcdecFault::hw_st_quad();
861 1: decode HW_LDST_QUAD {
862 format HwLoad {
863 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem_ul; }},
864 L, IsSerializing, IsSerializeBefore);
865 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem_uq; }},
866 Q, IsSerializing, IsSerializeBefore);

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917
918 0x1e: decode PALMODE {
919 0: OpcdecFault::hw_rei();
920 format BasicOperate {
921 1: hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
922 }
923 }
924
925 format BasicOperate {
926 // M5 special opcodes use the reserved 0x01 opcode space
927 0x01: decode M5FUNC {
928 0x00: arm({{
929 PseudoInst::arm(xc->tcBase());
930 }}, IsNonSpeculative);
931 0x01: quiesce({{
932 PseudoInst::quiesce(xc->tcBase());

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