branch.isa (7794:8a7ba5a1b35d) branch.isa (9552:460cf901acba)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2005 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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78 Branch(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
79 : PCDependentDisassembly(mnem, _machInst, __opClass),
80 disp(BRDISP << 2)
81 {
82 }
83
84 AlphaISA::PCState branchTarget(const AlphaISA::PCState &branchPC) const;
85
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2005 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 69 unchanged lines hidden (view full) ---

78 Branch(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
79 : PCDependentDisassembly(mnem, _machInst, __opClass),
80 disp(BRDISP << 2)
81 {
82 }
83
84 AlphaISA::PCState branchTarget(const AlphaISA::PCState &branchPC) const;
85
86 /// Explicitly import the otherwise hidden branchTarget
87 using StaticInst::branchTarget;
88
86 std::string
87 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
88 };
89
90 /**
91 * Base class for jumps (register-indirect control transfers). In
92 * the Alpha ISA, these are always unconditional.
93 */

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103 Jump(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
104 : PCDependentDisassembly(mnem, _machInst, __opClass),
105 disp(BRDISP)
106 {
107 }
108
109 AlphaISA::PCState branchTarget(ThreadContext *tc) const;
110
89 std::string
90 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
91 };
92
93 /**
94 * Base class for jumps (register-indirect control transfers). In
95 * the Alpha ISA, these are always unconditional.
96 */

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106 Jump(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
107 : PCDependentDisassembly(mnem, _machInst, __opClass),
108 disp(BRDISP)
109 {
110 }
111
112 AlphaISA::PCState branchTarget(ThreadContext *tc) const;
113
114 /// Explicitly import the otherwise hidden branchTarget
115 using StaticInst::branchTarget;
116
111 std::string
112 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
113 };
114}};
115
116output decoder {{
117 AlphaISA::PCState
118 Branch::branchTarget(const AlphaISA::PCState &branchPC) const

--- 156 unchanged lines hidden --- 		117 std::string
118 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
119 };
120}};
121
122output decoder {{
123 AlphaISA::PCState
124 Branch::branchTarget(const AlphaISA::PCState &branchPC) const

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