branch.isa (3953:300d526414e6) | branch.isa (7720:65d338a8dba4) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2003-2005 The Regents of The University of Michigan 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 67 unchanged lines hidden (view full) --- 76 77 /// Constructor. 78 Branch(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 79 : PCDependentDisassembly(mnem, _machInst, __opClass), 80 disp(BRDISP << 2) 81 { 82 } 83 | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2003-2005 The Regents of The University of Michigan 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 67 unchanged lines hidden (view full) --- 76 77 /// Constructor. 78 Branch(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 79 : PCDependentDisassembly(mnem, _machInst, __opClass), 80 disp(BRDISP << 2) 81 { 82 } 83 |
84 Addr branchTarget(Addr branchPC) const; | 84 AlphaISA::PCState branchTarget(const AlphaISA::PCState &branchPC) const; |
85 86 std::string 87 generateDisassembly(Addr pc, const SymbolTable *symtab) const; 88 }; 89 90 /** 91 * Base class for jumps (register-indirect control transfers). In 92 * the Alpha ISA, these are always unconditional. --- 8 unchanged lines hidden (view full) --- 101 public: 102 /// Constructor 103 Jump(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 104 : PCDependentDisassembly(mnem, _machInst, __opClass), 105 disp(BRDISP) 106 { 107 } 108 | 85 86 std::string 87 generateDisassembly(Addr pc, const SymbolTable *symtab) const; 88 }; 89 90 /** 91 * Base class for jumps (register-indirect control transfers). In 92 * the Alpha ISA, these are always unconditional. --- 8 unchanged lines hidden (view full) --- 101 public: 102 /// Constructor 103 Jump(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 104 : PCDependentDisassembly(mnem, _machInst, __opClass), 105 disp(BRDISP) 106 { 107 } 108 |
109 Addr branchTarget(ThreadContext *tc) const; | 109 AlphaISA::PCState branchTarget(ThreadContext *tc) const; |
110 111 std::string 112 generateDisassembly(Addr pc, const SymbolTable *symtab) const; 113 }; 114}}; 115 116output decoder {{ | 110 111 std::string 112 generateDisassembly(Addr pc, const SymbolTable *symtab) const; 113 }; 114}}; 115 116output decoder {{ |
117 Addr 118 Branch::branchTarget(Addr branchPC) const | 117 AlphaISA::PCState 118 Branch::branchTarget(const AlphaISA::PCState &branchPC) const |
119 { | 119 { |
120 return branchPC + 4 + disp; | 120 return branchPC.pc() + 4 + disp; |
121 } 122 | 121 } 122 |
123 Addr | 123 AlphaISA::PCState |
124 Jump::branchTarget(ThreadContext *tc) const 125 { | 124 Jump::branchTarget(ThreadContext *tc) const 125 { |
126 Addr NPC = tc->readPC() + 4; | 126 PCState pc = tc->pcState(); |
127 uint64_t Rb = tc->readIntReg(_srcRegIdx[0]); | 127 uint64_t Rb = tc->readIntReg(_srcRegIdx[0]); |
128 return (Rb & ~3) | (NPC & 1); | 128 pc.set((Rb & ~3) | (pc.pc() & 1)); 129 return pc; |
129 } 130 131 const std::string & 132 PCDependentDisassembly::disassemble(Addr pc, 133 const SymbolTable *symtab) const 134 { 135 if (!cachedDisassembly || 136 pc != cachedPC || symtab != cachedSymtab) --- 75 unchanged lines hidden (view full) --- 212 213def template JumpOrBranchDecode {{ 214 return (RA == 31) 215 ? (StaticInst *)new %(class_name)s(machInst) 216 : (StaticInst *)new %(class_name)sAndLink(machInst); 217}}; 218 219def format CondBranch(code) {{ | 130 } 131 132 const std::string & 133 PCDependentDisassembly::disassemble(Addr pc, 134 const SymbolTable *symtab) const 135 { 136 if (!cachedDisassembly || 137 pc != cachedPC || symtab != cachedSymtab) --- 75 unchanged lines hidden (view full) --- 213 214def template JumpOrBranchDecode {{ 215 return (RA == 31) 216 ? (StaticInst *)new %(class_name)s(machInst) 217 : (StaticInst *)new %(class_name)sAndLink(machInst); 218}}; 219 220def format CondBranch(code) {{ |
220 code = 'bool cond;\n' + code + '\nif (cond) NPC = NPC + disp;\n'; | 221 code = ''' 222 bool cond; 223 %(code)s; 224 PCState pc = PCS; 225 if (cond) 226 pc.npc(pc.npc() + disp); 227 PCS = pc; 228 ''' % { "code" : code } |
221 iop = InstObjParams(name, Name, 'Branch', code, 222 ('IsDirectControl', 'IsCondControl')) 223 header_output = BasicDeclare.subst(iop) 224 decoder_output = BasicConstructor.subst(iop) 225 decode_block = BasicDecode.subst(iop) 226 exec_output = BasicExecute.subst(iop) 227}}; 228 229let {{ 230def UncondCtrlBase(name, Name, base_class, npc_expr, flags): 231 # Declare basic control transfer w/o link (i.e. link reg is R31) | 229 iop = InstObjParams(name, Name, 'Branch', code, 230 ('IsDirectControl', 'IsCondControl')) 231 header_output = BasicDeclare.subst(iop) 232 decoder_output = BasicConstructor.subst(iop) 233 decode_block = BasicDecode.subst(iop) 234 exec_output = BasicExecute.subst(iop) 235}}; 236 237let {{ 238def UncondCtrlBase(name, Name, base_class, npc_expr, flags): 239 # Declare basic control transfer w/o link (i.e. link reg is R31) |
232 nolink_code = 'NPC = %s;\n' % npc_expr 233 nolink_iop = InstObjParams(name, Name, base_class, nolink_code, flags) | 240 readpc_code = 'PCState pc = PCS;' 241 nolink_code = 'pc.npc(%s);\nPCS = pc' % npc_expr 242 nolink_iop = InstObjParams(name, Name, base_class, 243 readpc_code + nolink_code, flags) |
234 header_output = BasicDeclare.subst(nolink_iop) 235 decoder_output = BasicConstructor.subst(nolink_iop) 236 exec_output = BasicExecute.subst(nolink_iop) 237 238 # Generate declaration of '*AndLink' version, append to decls | 244 header_output = BasicDeclare.subst(nolink_iop) 245 decoder_output = BasicConstructor.subst(nolink_iop) 246 exec_output = BasicExecute.subst(nolink_iop) 247 248 # Generate declaration of '*AndLink' version, append to decls |
239 link_code = 'Ra = NPC & ~3;\n' + nolink_code | 249 link_code = 'Ra = pc.npc() & ~3;\n' + nolink_code |
240 link_iop = InstObjParams(name, Name + 'AndLink', base_class, | 250 link_iop = InstObjParams(name, Name + 'AndLink', base_class, |
241 link_code, flags) | 251 readpc_code + link_code, flags) |
242 header_output += BasicDeclare.subst(link_iop) 243 decoder_output += BasicConstructor.subst(link_iop) 244 exec_output += BasicExecute.subst(link_iop) 245 246 # need to use link_iop for the decode template since it is expecting 247 # the shorter version of class_name (w/o "AndLink") 248 249 return (header_output, decoder_output, 250 JumpOrBranchDecode.subst(nolink_iop), exec_output) 251}}; 252 253def format UncondBranch(*flags) {{ 254 flags += ('IsUncondControl', 'IsDirectControl') 255 (header_output, decoder_output, decode_block, exec_output) = \ | 252 header_output += BasicDeclare.subst(link_iop) 253 decoder_output += BasicConstructor.subst(link_iop) 254 exec_output += BasicExecute.subst(link_iop) 255 256 # need to use link_iop for the decode template since it is expecting 257 # the shorter version of class_name (w/o "AndLink") 258 259 return (header_output, decoder_output, 260 JumpOrBranchDecode.subst(nolink_iop), exec_output) 261}}; 262 263def format UncondBranch(*flags) {{ 264 flags += ('IsUncondControl', 'IsDirectControl') 265 (header_output, decoder_output, decode_block, exec_output) = \ |
256 UncondCtrlBase(name, Name, 'Branch', 'NPC + disp', flags) | 266 UncondCtrlBase(name, Name, 'Branch', 'pc.npc() + disp', flags) |
257}}; 258 259def format Jump(*flags) {{ 260 flags += ('IsUncondControl', 'IsIndirectControl') 261 (header_output, decoder_output, decode_block, exec_output) = \ | 267}}; 268 269def format Jump(*flags) {{ 270 flags += ('IsUncondControl', 'IsIndirectControl') 271 (header_output, decoder_output, decode_block, exec_output) = \ |
262 UncondCtrlBase(name, Name, 'Jump', '(Rb & ~3) | (NPC & 1)', flags) | 272 UncondCtrlBase(name, Name, 'Jump', '(Rb & ~3) | (pc.npc() & 1)', flags) |
263}}; 264 265 | 273}}; 274 275 |