1// -*- mode:c++ -*- 2 3// Copyright (c) 2003-2005 The Regents of The University of Michigan 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 67 unchanged lines hidden (view full) --- 76 77 /// Constructor. 78 Branch(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 79 : PCDependentDisassembly(mnem, _machInst, __opClass), 80 disp(BRDISP << 2) 81 { 82 } 83 |
84 AlphaISA::PCState branchTarget( 85 const AlphaISA::PCState &branchPC) const override; |
86 87 /// Explicitly import the otherwise hidden branchTarget 88 using StaticInst::branchTarget; 89 |
90 std::string generateDisassembly( 91 Addr pc, const SymbolTable *symtab) const override; |
92 }; 93 94 /** 95 * Base class for jumps (register-indirect control transfers). In 96 * the Alpha ISA, these are always unconditional. 97 */ 98 class Jump : public PCDependentDisassembly 99 { --- 5 unchanged lines hidden (view full) --- 105 public: 106 /// Constructor 107 Jump(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 108 : PCDependentDisassembly(mnem, _machInst, __opClass), 109 disp(BRDISP) 110 { 111 } 112 |
113 AlphaISA::PCState branchTarget(ThreadContext *tc) const override; |
114 115 /// Explicitly import the otherwise hidden branchTarget 116 using StaticInst::branchTarget; 117 |
118 std::string generateDisassembly( 119 Addr pc, const SymbolTable *symtab) const override; |
120 }; 121}}; 122 123output decoder {{ 124 AlphaISA::PCState 125 Branch::branchTarget(const AlphaISA::PCState &branchPC) const 126 { 127 return branchPC.pc() + 4 + disp; --- 154 unchanged lines hidden --- |