isa.hh (6313:95f69a436c82) isa.hh (6330:786136379872)
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_ALPHA_ISA_HH__
32#define __ARCH_ALPHA_ISA_HH__
33
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 17 unchanged lines hidden (view full) ---

26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_ALPHA_ISA_HH__
32#define __ARCH_ALPHA_ISA_HH__
33
34#include "arch/alpha/miscregfile.hh"
34#include <string>
35#include <iostream>
36
37#include "arch/alpha/registers.hh"
35#include "arch/alpha/types.hh"
38#include "arch/alpha/types.hh"
39#include "base/types.hh"
36
40
41class BaseCPU;
37class Checkpoint;
38class EventManager;
42class Checkpoint;
43class EventManager;
44class ThreadContext;
39
40namespace AlphaISA
41{
42 class ISA
43 {
45
46namespace AlphaISA
47{
48 class ISA
49 {
50 public:
51 typedef uint64_t InternalProcReg;
52
44 protected:
53 protected:
45 MiscRegFile miscRegFile;
54 uint64_t fpcr; // floating point condition codes
55 uint64_t uniq; // process-unique register
56 bool lock_flag; // lock flag for LL/SC
57 Addr lock_addr; // lock address for LL/SC
58 int intr_flag;
46
59
60 InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
61
62 protected:
63 InternalProcReg readIpr(int idx, ThreadContext *tc);
64 void setIpr(int idx, InternalProcReg val, ThreadContext *tc);
65
47 public:
48
66 public:
67
49 void expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
50 {
51 miscRegFile.expandForMultithreading(num_threads, num_vpes);
52 }
68 // These functions should be removed once the simplescalar cpu
69 // model has been replaced.
70 int getInstAsid();
71 int getDataAsid();
53
72
54 void reset(std::string core_name, ThreadID num_threads,
55 unsigned num_vpes, BaseCPU *_cpu)
56 {
57 miscRegFile.reset(core_name, num_threads, num_vpes, _cpu);
58 }
73 MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
74 MiscReg readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
59
75
60 int instAsid()
61 {
62 return miscRegFile.getInstAsid();
63 }
76 void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
77 ThreadID tid = 0);
78 void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
79 ThreadID tid = 0);
64
80
65 int dataAsid()
81 void
82 clear()
66 {
83 {
67 return miscRegFile.getDataAsid();
84 fpcr = 0;
85 uniq = 0;
86 lock_flag = 0;
87 lock_addr = 0;
88 intr_flag = 0;
68 }
69
89 }
90
70 void clear();
91 void serialize(std::ostream &os);
92 void unserialize(Checkpoint *cp, const std::string &section);
71
93
72 MiscReg readMiscRegNoEffect(int miscReg);
73 MiscReg readMiscReg(int miscReg, ThreadContext *tc);
94 void reset(std::string core_name, ThreadID num_threads,
95 unsigned num_vpes, BaseCPU *_cpu)
96 { }
74
97
75 void setMiscRegNoEffect(int miscReg, const MiscReg val);
76 void setMiscReg(int miscReg, const MiscReg val,
77 ThreadContext *tc);
78
98
99 void expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
100 { }
101
79 int
80 flattenIntIndex(int reg)
81 {
82 return reg;
83 }
84
85 int
86 flattenFloatIndex(int reg)
87 {
88 return reg;
89 }
90
102 int
103 flattenIntIndex(int reg)
104 {
105 return reg;
106 }
107
108 int
109 flattenFloatIndex(int reg)
110 {
111 return reg;
112 }
113
91 void serialize(std::ostream &os);
92 void unserialize(Checkpoint *cp, const std::string &section);
93
94 ISA()
95 {
96 clear();
114 ISA()
115 {
116 clear();
117 initializeIprTable();
97 }
98 };
99}
100
101#endif
118 }
119 };
120}
121
122#endif