isa.hh (11168:f98eb2da15a4) | isa.hh (12106:7784fac1b159) |
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1/* 2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 24 unchanged lines hidden (view full) --- 33 34#include <cstring> 35#include <iostream> 36#include <string> 37 38#include "arch/alpha/registers.hh" 39#include "arch/alpha/types.hh" 40#include "base/types.hh" | 1/* 2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 24 unchanged lines hidden (view full) --- 33 34#include <cstring> 35#include <iostream> 36#include <string> 37 38#include "arch/alpha/registers.hh" 39#include "arch/alpha/types.hh" 40#include "base/types.hh" |
41#include "cpu/reg_class.hh" |
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41#include "sim/sim_object.hh" 42#include "sim/system.hh" 43 44struct AlphaISAParams; 45class BaseCPU; 46class Checkpoint; 47class EventManager; 48class ThreadContext; --- 41 unchanged lines hidden (view full) --- 90 lock_addr = 0; 91 intr_flag = 0; 92 memset(ipr, 0, sizeof(ipr)); 93 } 94 95 void serialize(CheckpointOut &cp) const override; 96 void unserialize(CheckpointIn &cp) override; 97 | 42#include "sim/sim_object.hh" 43#include "sim/system.hh" 44 45struct AlphaISAParams; 46class BaseCPU; 47class Checkpoint; 48class EventManager; 49class ThreadContext; --- 41 unchanged lines hidden (view full) --- 91 lock_addr = 0; 92 intr_flag = 0; 93 memset(ipr, 0, sizeof(ipr)); 94 } 95 96 void serialize(CheckpointOut &cp) const override; 97 void unserialize(CheckpointIn &cp) override; 98 |
99 RegId flattenRegId(const RegId& regId) const { return regId; } 100 |
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98 int 99 flattenIntIndex(int reg) const 100 { 101 return reg; 102 } 103 104 int 105 flattenFloatIndex(int reg) const --- 29 unchanged lines hidden --- | 101 int 102 flattenIntIndex(int reg) const 103 { 104 return reg; 105 } 106 107 int 108 flattenFloatIndex(int reg) const --- 29 unchanged lines hidden --- |