1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_ALPHA_ISA_HH__
32#define __ARCH_ALPHA_ISA_HH__
33
|
37
38#include "arch/alpha/registers.hh"
39#include "arch/alpha/types.hh"
40#include "base/types.hh"
41
42class BaseCPU;
43class Checkpoint;
44class EventManager;
45class ThreadContext;
46
47namespace AlphaISA
48{
49 class ISA
50 {
51 public:
52 typedef uint64_t InternalProcReg;
53
54 protected:
55 uint64_t fpcr; // floating point condition codes
56 uint64_t uniq; // process-unique register
57 bool lock_flag; // lock flag for LL/SC
58 Addr lock_addr; // lock address for LL/SC
59 int intr_flag;
60
61 InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
62
63 protected:
64 InternalProcReg readIpr(int idx, ThreadContext *tc);
65 void setIpr(int idx, InternalProcReg val, ThreadContext *tc);
66
67 public:
68
69 MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
70 MiscReg readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
71
72 void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
73 ThreadID tid = 0);
74 void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
75 ThreadID tid = 0);
76
77 void
78 clear()
79 {
80 fpcr = 0;
81 uniq = 0;
82 lock_flag = 0;
83 lock_addr = 0;
84 intr_flag = 0;
85 memset(ipr, 0, sizeof(ipr));
86 }
87
88 void serialize(EventManager *em, std::ostream &os);
89 void unserialize(EventManager *em, Checkpoint *cp,
90 const std::string §ion);
91
92 int
93 flattenIntIndex(int reg)
94 {
95 return reg;
96 }
97
98 int
99 flattenFloatIndex(int reg)
100 {
101 return reg;
102 }
103
104 ISA()
105 {
106 clear();
107 initializeIprTable();
108 }
109 };
110}
111
112#endif
|