isa.hh (9553:2e1e5364dae3) isa.hh (9920:028e4da64b42)
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_ALPHA_ISA_HH__
32#define __ARCH_ALPHA_ISA_HH__
33
34#include <cstring>
35#include <iostream>
36#include <string>
37
38#include "arch/alpha/registers.hh"
39#include "arch/alpha/types.hh"
40#include "base/types.hh"
41#include "sim/sim_object.hh"
42
43struct AlphaISAParams;
44class BaseCPU;
45class Checkpoint;
46class EventManager;
47class ThreadContext;
48
49namespace AlphaISA
50{
51 class ISA : public SimObject
52 {
53 public:
54 typedef uint64_t InternalProcReg;
55 typedef AlphaISAParams Params;
56
57 protected:
58 uint64_t fpcr; // floating point condition codes
59 uint64_t uniq; // process-unique register
60 bool lock_flag; // lock flag for LL/SC
61 Addr lock_addr; // lock address for LL/SC
62 int intr_flag;
63
64 InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
65
66 protected:
67 InternalProcReg readIpr(int idx, ThreadContext *tc);
68 void setIpr(int idx, InternalProcReg val, ThreadContext *tc);
69
70 public:
71
72 MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
73 MiscReg readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
74
75 void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
76 ThreadID tid = 0);
77 void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
78 ThreadID tid = 0);
79
80 void
81 clear()
82 {
83 fpcr = 0;
84 uniq = 0;
85 lock_flag = 0;
86 lock_addr = 0;
87 intr_flag = 0;
88 memset(ipr, 0, sizeof(ipr));
89 }
90
91 void serialize(std::ostream &os);
92 void unserialize(Checkpoint *cp, const std::string &section);
93
94 int
95 flattenIntIndex(int reg)
96 {
97 return reg;
98 }
99
100 int
101 flattenFloatIndex(int reg)
102 {
103 return reg;
104 }
105
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_ALPHA_ISA_HH__
32#define __ARCH_ALPHA_ISA_HH__
33
34#include <cstring>
35#include <iostream>
36#include <string>
37
38#include "arch/alpha/registers.hh"
39#include "arch/alpha/types.hh"
40#include "base/types.hh"
41#include "sim/sim_object.hh"
42
43struct AlphaISAParams;
44class BaseCPU;
45class Checkpoint;
46class EventManager;
47class ThreadContext;
48
49namespace AlphaISA
50{
51 class ISA : public SimObject
52 {
53 public:
54 typedef uint64_t InternalProcReg;
55 typedef AlphaISAParams Params;
56
57 protected:
58 uint64_t fpcr; // floating point condition codes
59 uint64_t uniq; // process-unique register
60 bool lock_flag; // lock flag for LL/SC
61 Addr lock_addr; // lock address for LL/SC
62 int intr_flag;
63
64 InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
65
66 protected:
67 InternalProcReg readIpr(int idx, ThreadContext *tc);
68 void setIpr(int idx, InternalProcReg val, ThreadContext *tc);
69
70 public:
71
72 MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
73 MiscReg readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
74
75 void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
76 ThreadID tid = 0);
77 void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
78 ThreadID tid = 0);
79
80 void
81 clear()
82 {
83 fpcr = 0;
84 uniq = 0;
85 lock_flag = 0;
86 lock_addr = 0;
87 intr_flag = 0;
88 memset(ipr, 0, sizeof(ipr));
89 }
90
91 void serialize(std::ostream &os);
92 void unserialize(Checkpoint *cp, const std::string &section);
93
94 int
95 flattenIntIndex(int reg)
96 {
97 return reg;
98 }
99
100 int
101 flattenFloatIndex(int reg)
102 {
103 return reg;
104 }
105
106 // dummy
107 int
108 flattenCCIndex(int reg)
109 {
110 return reg;
111 }
112
106 const Params *params() const;
107
108 ISA(Params *p);
109
110 void startup(ThreadContext *tc) {}
111
112 /// Explicitly import the otherwise hidden startup
113 using SimObject::startup;
114 };
115}
116
117#endif
113 const Params *params() const;
114
115 ISA(Params *p);
116
117 void startup(ThreadContext *tc) {}
118
119 /// Explicitly import the otherwise hidden startup
120 using SimObject::startup;
121 };
122}
123
124#endif