1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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33
34#include <cstring>
35#include <iostream>
36#include <string>
37
38#include "arch/alpha/registers.hh"
39#include "arch/alpha/types.hh"
40#include "base/types.hh"
41#include "sim/sim_object.hh"
42#include "sim/system.hh"
43
44struct AlphaISAParams;
45class BaseCPU;
46class Checkpoint;
47class EventManager;
48class ThreadContext;

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90 lock_addr = 0;
91 intr_flag = 0;
92 memset(ipr, 0, sizeof(ipr));
93 }
94
95 void serialize(CheckpointOut &cp) const override;
96 void unserialize(CheckpointIn &cp) override;
97
98 int
99 flattenIntIndex(int reg) const
100 {
101 return reg;
102 }
103
104 int
105 flattenFloatIndex(int reg) const

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