isa.cc (13582:989577bf6abc) isa.cc (13614:52c5311db96b)
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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69 UNSERIALIZE_SCALAR(fpcr);
70 UNSERIALIZE_SCALAR(uniq);
71 UNSERIALIZE_SCALAR(lock_flag);
72 UNSERIALIZE_SCALAR(lock_addr);
73 UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs);
74}
75
76
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 60 unchanged lines hidden (view full) ---

69 UNSERIALIZE_SCALAR(fpcr);
70 UNSERIALIZE_SCALAR(uniq);
71 UNSERIALIZE_SCALAR(lock_flag);
72 UNSERIALIZE_SCALAR(lock_addr);
73 UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs);
74}
75
76
77MiscReg
77RegVal
78ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
79{
80 switch (misc_reg) {
81 case MISCREG_FPCR:
82 return fpcr;
83 case MISCREG_UNIQ:
84 return uniq;
85 case MISCREG_LOCKFLAG:
86 return lock_flag;
87 case MISCREG_LOCKADDR:
88 return lock_addr;
89 case MISCREG_INTR:
90 return intr_flag;
91 default:
92 assert(misc_reg < NumInternalProcRegs);
93 return ipr[misc_reg];
94 }
95}
96
78ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
79{
80 switch (misc_reg) {
81 case MISCREG_FPCR:
82 return fpcr;
83 case MISCREG_UNIQ:
84 return uniq;
85 case MISCREG_LOCKFLAG:
86 return lock_flag;
87 case MISCREG_LOCKADDR:
88 return lock_addr;
89 case MISCREG_INTR:
90 return intr_flag;
91 default:
92 assert(misc_reg < NumInternalProcRegs);
93 return ipr[misc_reg];
94 }
95}
96
97MiscReg
97RegVal
98ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
99{
100 switch (misc_reg) {
101 case MISCREG_FPCR:
102 return fpcr;
103 case MISCREG_UNIQ:
104 return uniq;
105 case MISCREG_LOCKFLAG:
106 return lock_flag;
107 case MISCREG_LOCKADDR:
108 return lock_addr;
109 case MISCREG_INTR:
110 return intr_flag;
111 default:
112 return readIpr(misc_reg, tc);
113 }
114}
115
116void
98ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
99{
100 switch (misc_reg) {
101 case MISCREG_FPCR:
102 return fpcr;
103 case MISCREG_UNIQ:
104 return uniq;
105 case MISCREG_LOCKFLAG:
106 return lock_flag;
107 case MISCREG_LOCKADDR:
108 return lock_addr;
109 case MISCREG_INTR:
110 return intr_flag;
111 default:
112 return readIpr(misc_reg, tc);
113 }
114}
115
116void
117ISA::setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid)
117ISA::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
118{
119 switch (misc_reg) {
120 case MISCREG_FPCR:
121 fpcr = val;
122 return;
123 case MISCREG_UNIQ:
124 uniq = val;
125 return;

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135 default:
136 assert(misc_reg < NumInternalProcRegs);
137 ipr[misc_reg] = val;
138 return;
139 }
140}
141
142void
118{
119 switch (misc_reg) {
120 case MISCREG_FPCR:
121 fpcr = val;
122 return;
123 case MISCREG_UNIQ:
124 uniq = val;
125 return;

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135 default:
136 assert(misc_reg < NumInternalProcRegs);
137 ipr[misc_reg] = val;
138 return;
139 }
140}
141
142void
143ISA::setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc, ThreadID tid)
143ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc, ThreadID tid)
144{
145 switch (misc_reg) {
146 case MISCREG_FPCR:
147 fpcr = val;
148 return;
149 case MISCREG_UNIQ:
150 uniq = val;
151 return;

--- 22 unchanged lines hidden --- 		144{
145 switch (misc_reg) {
146 case MISCREG_FPCR:
147 fpcr = val;
148 return;
149 case MISCREG_UNIQ:
150 uniq = val;
151 return;

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