1/* 2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 15 unchanged lines hidden (view full) --- 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#include "arch/alpha/isa.hh" |
32#include "base/misc.hh" |
33#include "cpu/thread_context.hh" 34 35namespace AlphaISA 36{ 37 38void |
39ISA::serialize(std::ostream &os) |
40{ |
41 SERIALIZE_SCALAR(fpcr); 42 SERIALIZE_SCALAR(uniq); 43 SERIALIZE_SCALAR(lock_flag); 44 SERIALIZE_SCALAR(lock_addr); 45 SERIALIZE_ARRAY(ipr, NumInternalProcRegs); |
46} 47 |
48void 49ISA::unserialize(Checkpoint *cp, const std::string §ion) |
50{ |
51 UNSERIALIZE_SCALAR(fpcr); 52 UNSERIALIZE_SCALAR(uniq); 53 UNSERIALIZE_SCALAR(lock_flag); 54 UNSERIALIZE_SCALAR(lock_addr); 55 UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs); |
56} 57 |
58 |
59MiscReg |
60ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) |
61{ |
62 switch (misc_reg) { 63 case MISCREG_FPCR: 64 return fpcr; 65 case MISCREG_UNIQ: 66 return uniq; 67 case MISCREG_LOCKFLAG: 68 return lock_flag; 69 case MISCREG_LOCKADDR: 70 return lock_addr; 71 case MISCREG_INTR: 72 return intr_flag; 73 default: 74 assert(misc_reg < NumInternalProcRegs); 75 return ipr[misc_reg]; 76 } |
77} 78 |
79MiscReg 80ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid) |
81{ |
82 switch (misc_reg) { 83 case MISCREG_FPCR: 84 return fpcr; 85 case MISCREG_UNIQ: 86 return uniq; 87 case MISCREG_LOCKFLAG: 88 return lock_flag; 89 case MISCREG_LOCKADDR: 90 return lock_addr; 91 case MISCREG_INTR: 92 return intr_flag; 93 default: 94 return readIpr(misc_reg, tc); 95 } |
96} 97 98void |
99ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid) |
100{ |
101 switch (misc_reg) { 102 case MISCREG_FPCR: 103 fpcr = val; 104 return; 105 case MISCREG_UNIQ: 106 uniq = val; 107 return; 108 case MISCREG_LOCKFLAG: 109 lock_flag = val; 110 return; 111 case MISCREG_LOCKADDR: 112 lock_addr = val; 113 return; 114 case MISCREG_INTR: 115 intr_flag = val; 116 return; 117 default: 118 assert(misc_reg < NumInternalProcRegs); 119 ipr[misc_reg] = val; 120 return; 121 } |
122} 123 124void |
125ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc, 126 ThreadID tid) |
127{ |
128 switch (misc_reg) { 129 case MISCREG_FPCR: 130 fpcr = val; 131 return; 132 case MISCREG_UNIQ: 133 uniq = val; 134 return; 135 case MISCREG_LOCKFLAG: 136 lock_flag = val; 137 return; 138 case MISCREG_LOCKADDR: 139 lock_addr = val; 140 return; 141 case MISCREG_INTR: 142 intr_flag = val; 143 return; 144 default: 145 setIpr(misc_reg, val, tc); 146 return; 147 } |
148} 149 |
150} |