31a32
> #include "base/misc.hh"
38c39
< ISA::clear()
---
> ISA::serialize(std::ostream &os)
40c41,45
< miscRegFile.clear();
---
> SERIALIZE_SCALAR(fpcr);
> SERIALIZE_SCALAR(uniq);
> SERIALIZE_SCALAR(lock_flag);
> SERIALIZE_SCALAR(lock_addr);
> SERIALIZE_ARRAY(ipr, NumInternalProcRegs);
43,44c48,49
< MiscReg
< ISA::readMiscRegNoEffect(int miscReg)
---
> void
> ISA::unserialize(Checkpoint *cp, const std::string &section)
46c51,55
< return miscRegFile.readRegNoEffect((MiscRegIndex)miscReg);
---
> UNSERIALIZE_SCALAR(fpcr);
> UNSERIALIZE_SCALAR(uniq);
> UNSERIALIZE_SCALAR(lock_flag);
> UNSERIALIZE_SCALAR(lock_addr);
> UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs);
48a58
>
50c60
< ISA::readMiscReg(int miscReg, ThreadContext *tc)
---
> ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid)
52c62,76
< return miscRegFile.readReg((MiscRegIndex)miscReg, tc);
---
> switch (misc_reg) {
> case MISCREG_FPCR:
> return fpcr;
> case MISCREG_UNIQ:
> return uniq;
> case MISCREG_LOCKFLAG:
> return lock_flag;
> case MISCREG_LOCKADDR:
> return lock_addr;
> case MISCREG_INTR:
> return intr_flag;
> default:
> assert(misc_reg < NumInternalProcRegs);
> return ipr[misc_reg];
> }
55,56c79,80
< void
< ISA::setMiscRegNoEffect(int miscReg, const MiscReg val)
---
> MiscReg
> ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
58c82,95
< miscRegFile.setRegNoEffect((MiscRegIndex)miscReg, val);
---
> switch (misc_reg) {
> case MISCREG_FPCR:
> return fpcr;
> case MISCREG_UNIQ:
> return uniq;
> case MISCREG_LOCKFLAG:
> return lock_flag;
> case MISCREG_LOCKADDR:
> return lock_addr;
> case MISCREG_INTR:
> return intr_flag;
> default:
> return readIpr(misc_reg, tc);
> }
62c99
< ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc)
---
> ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
64c101,121
< miscRegFile.setReg((MiscRegIndex)miscReg, val, tc);
---
> switch (misc_reg) {
> case MISCREG_FPCR:
> fpcr = val;
> return;
> case MISCREG_UNIQ:
> uniq = val;
> return;
> case MISCREG_LOCKFLAG:
> lock_flag = val;
> return;
> case MISCREG_LOCKADDR:
> lock_addr = val;
> return;
> case MISCREG_INTR:
> intr_flag = val;
> return;
> default:
> assert(misc_reg < NumInternalProcRegs);
> ipr[misc_reg] = val;
> return;
> }
68c125,126
< ISA::serialize(std::ostream &os)
---
> ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
> ThreadID tid)
70c128,147
< miscRegFile.serialize(os);
---
> switch (misc_reg) {
> case MISCREG_FPCR:
> fpcr = val;
> return;
> case MISCREG_UNIQ:
> uniq = val;
> return;
> case MISCREG_LOCKFLAG:
> lock_flag = val;
> return;
> case MISCREG_LOCKADDR:
> lock_addr = val;
> return;
> case MISCREG_INTR:
> intr_flag = val;
> return;
> default:
> setIpr(misc_reg, val, tc);
> return;
> }
73,76d149
< void
< ISA::unserialize(Checkpoint *cp, const std::string &section)
< {
< miscRegFile.unserialize(cp, section);
78,79d150
<
< }