1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include <cassert>
32
33#include "arch/alpha/isa.hh"
34#include "base/misc.hh"
35#include "cpu/thread_context.hh"
| 1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include <cassert>
32
33#include "arch/alpha/isa.hh"
34#include "base/misc.hh"
35#include "cpu/thread_context.hh"
|
| 36#include "params/AlphaISA.hh"
|
36#include "sim/serialize.hh"
37
38namespace AlphaISA
39{
40
| 37#include "sim/serialize.hh"
38
39namespace AlphaISA
40{
41
|
| 42ISA::ISA(Params *p)
43 : SimObject(p)
44{
45 clear();
46 initializeIprTable();
47}
48
49const AlphaISAParams *
50ISA::params() const
51{
52 return dynamic_cast<const Params *>(_params);
53}
54
|
41void
42ISA::serialize(EventManager *em, std::ostream &os)
43{
44 SERIALIZE_SCALAR(fpcr);
45 SERIALIZE_SCALAR(uniq);
46 SERIALIZE_SCALAR(lock_flag);
47 SERIALIZE_SCALAR(lock_addr);
48 SERIALIZE_ARRAY(ipr, NumInternalProcRegs);
49}
50
51void
52ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string §ion)
53{
54 UNSERIALIZE_SCALAR(fpcr);
55 UNSERIALIZE_SCALAR(uniq);
56 UNSERIALIZE_SCALAR(lock_flag);
57 UNSERIALIZE_SCALAR(lock_addr);
58 UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs);
59}
60
61
62MiscReg
63ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid)
64{
65 switch (misc_reg) {
66 case MISCREG_FPCR:
67 return fpcr;
68 case MISCREG_UNIQ:
69 return uniq;
70 case MISCREG_LOCKFLAG:
71 return lock_flag;
72 case MISCREG_LOCKADDR:
73 return lock_addr;
74 case MISCREG_INTR:
75 return intr_flag;
76 default:
77 assert(misc_reg < NumInternalProcRegs);
78 return ipr[misc_reg];
79 }
80}
81
82MiscReg
83ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
84{
85 switch (misc_reg) {
86 case MISCREG_FPCR:
87 return fpcr;
88 case MISCREG_UNIQ:
89 return uniq;
90 case MISCREG_LOCKFLAG:
91 return lock_flag;
92 case MISCREG_LOCKADDR:
93 return lock_addr;
94 case MISCREG_INTR:
95 return intr_flag;
96 default:
97 return readIpr(misc_reg, tc);
98 }
99}
100
101void
102ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
103{
104 switch (misc_reg) {
105 case MISCREG_FPCR:
106 fpcr = val;
107 return;
108 case MISCREG_UNIQ:
109 uniq = val;
110 return;
111 case MISCREG_LOCKFLAG:
112 lock_flag = val;
113 return;
114 case MISCREG_LOCKADDR:
115 lock_addr = val;
116 return;
117 case MISCREG_INTR:
118 intr_flag = val;
119 return;
120 default:
121 assert(misc_reg < NumInternalProcRegs);
122 ipr[misc_reg] = val;
123 return;
124 }
125}
126
127void
128ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
129 ThreadID tid)
130{
131 switch (misc_reg) {
132 case MISCREG_FPCR:
133 fpcr = val;
134 return;
135 case MISCREG_UNIQ:
136 uniq = val;
137 return;
138 case MISCREG_LOCKFLAG:
139 lock_flag = val;
140 return;
141 case MISCREG_LOCKADDR:
142 lock_addr = val;
143 return;
144 case MISCREG_INTR:
145 intr_flag = val;
146 return;
147 default:
148 setIpr(misc_reg, val, tc);
149 return;
150 }
151}
152
153}
| 55void
56ISA::serialize(EventManager *em, std::ostream &os)
57{
58 SERIALIZE_SCALAR(fpcr);
59 SERIALIZE_SCALAR(uniq);
60 SERIALIZE_SCALAR(lock_flag);
61 SERIALIZE_SCALAR(lock_addr);
62 SERIALIZE_ARRAY(ipr, NumInternalProcRegs);
63}
64
65void
66ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string §ion)
67{
68 UNSERIALIZE_SCALAR(fpcr);
69 UNSERIALIZE_SCALAR(uniq);
70 UNSERIALIZE_SCALAR(lock_flag);
71 UNSERIALIZE_SCALAR(lock_addr);
72 UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs);
73}
74
75
76MiscReg
77ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid)
78{
79 switch (misc_reg) {
80 case MISCREG_FPCR:
81 return fpcr;
82 case MISCREG_UNIQ:
83 return uniq;
84 case MISCREG_LOCKFLAG:
85 return lock_flag;
86 case MISCREG_LOCKADDR:
87 return lock_addr;
88 case MISCREG_INTR:
89 return intr_flag;
90 default:
91 assert(misc_reg < NumInternalProcRegs);
92 return ipr[misc_reg];
93 }
94}
95
96MiscReg
97ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
98{
99 switch (misc_reg) {
100 case MISCREG_FPCR:
101 return fpcr;
102 case MISCREG_UNIQ:
103 return uniq;
104 case MISCREG_LOCKFLAG:
105 return lock_flag;
106 case MISCREG_LOCKADDR:
107 return lock_addr;
108 case MISCREG_INTR:
109 return intr_flag;
110 default:
111 return readIpr(misc_reg, tc);
112 }
113}
114
115void
116ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
117{
118 switch (misc_reg) {
119 case MISCREG_FPCR:
120 fpcr = val;
121 return;
122 case MISCREG_UNIQ:
123 uniq = val;
124 return;
125 case MISCREG_LOCKFLAG:
126 lock_flag = val;
127 return;
128 case MISCREG_LOCKADDR:
129 lock_addr = val;
130 return;
131 case MISCREG_INTR:
132 intr_flag = val;
133 return;
134 default:
135 assert(misc_reg < NumInternalProcRegs);
136 ipr[misc_reg] = val;
137 return;
138 }
139}
140
141void
142ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
143 ThreadID tid)
144{
145 switch (misc_reg) {
146 case MISCREG_FPCR:
147 fpcr = val;
148 return;
149 case MISCREG_UNIQ:
150 uniq = val;
151 return;
152 case MISCREG_LOCKFLAG:
153 lock_flag = val;
154 return;
155 case MISCREG_LOCKADDR:
156 lock_addr = val;
157 return;
158 case MISCREG_INTR:
159 intr_flag = val;
160 return;
161 default:
162 setIpr(misc_reg, val, tc);
163 return;
164 }
165}
166
167}
|
| 168
169AlphaISA::ISA *
170AlphaISAParams::create()
171{
172 return new AlphaISA::ISA(this);
173}
|
| |