1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include <cassert>
32
33#include "arch/alpha/isa.hh"
34#include "base/misc.hh"
35#include "cpu/thread_context.hh"
36
37namespace AlphaISA
38{
39
40void
41ISA::serialize(EventManager *em, std::ostream &os)
42{
43 SERIALIZE_SCALAR(fpcr);
44 SERIALIZE_SCALAR(uniq);
45 SERIALIZE_SCALAR(lock_flag);
46 SERIALIZE_SCALAR(lock_addr);
47 SERIALIZE_ARRAY(ipr, NumInternalProcRegs);
48}
49
50void
51ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string &section)
52{
53 UNSERIALIZE_SCALAR(fpcr);
54 UNSERIALIZE_SCALAR(uniq);
55 UNSERIALIZE_SCALAR(lock_flag);
56 UNSERIALIZE_SCALAR(lock_addr);
57 UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs);
58}
59
60
61MiscReg
62ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid)
63{
64 switch (misc_reg) {
65 case MISCREG_FPCR:
66 return fpcr;
67 case MISCREG_UNIQ:
68 return uniq;
69 case MISCREG_LOCKFLAG:
70 return lock_flag;
71 case MISCREG_LOCKADDR:
72 return lock_addr;
73 case MISCREG_INTR:
74 return intr_flag;
75 default:
76 assert(misc_reg < NumInternalProcRegs);
77 return ipr[misc_reg];
78 }
79}
80
81MiscReg
82ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
83{
84 switch (misc_reg) {
85 case MISCREG_FPCR:
86 return fpcr;
87 case MISCREG_UNIQ:
88 return uniq;
89 case MISCREG_LOCKFLAG:
90 return lock_flag;
91 case MISCREG_LOCKADDR:
92 return lock_addr;
93 case MISCREG_INTR:
94 return intr_flag;
95 default:
96 return readIpr(misc_reg, tc);
97 }
98}
99
100void
101ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
102{
103 switch (misc_reg) {
104 case MISCREG_FPCR:
105 fpcr = val;
106 return;
107 case MISCREG_UNIQ:
108 uniq = val;
109 return;
110 case MISCREG_LOCKFLAG:
111 lock_flag = val;
112 return;
113 case MISCREG_LOCKADDR:
114 lock_addr = val;
115 return;
116 case MISCREG_INTR:
117 intr_flag = val;
118 return;
119 default:
120 assert(misc_reg < NumInternalProcRegs);
121 ipr[misc_reg] = val;
122 return;
123 }
124}
125
126void
127ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
128 ThreadID tid)
129{
130 switch (misc_reg) {
131 case MISCREG_FPCR:
132 fpcr = val;
133 return;
134 case MISCREG_UNIQ:
135 uniq = val;
136 return;
137 case MISCREG_LOCKFLAG:
138 lock_flag = val;
139 return;
140 case MISCREG_LOCKADDR:
141 lock_addr = val;
142 return;
143 case MISCREG_INTR:
144 intr_flag = val;
145 return;
146 default:
147 setIpr(misc_reg, val, tc);
148 return;
149 }
150}
151
152}