ipr.hh (5543:3af77710f397) ipr.hh (5569:baeee670d4ce)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 18 unchanged lines hidden (view full) ---

27 *
28 * Authors: Steve Reinhardt
29 * Gabe Black
30 */
31
32#ifndef __ARCH_ALPHA_IPR_HH__
33#define __ARCH_ALPHA_IPR_HH__
34
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 18 unchanged lines hidden (view full) ---

27 *
28 * Authors: Steve Reinhardt
29 * Gabe Black
30 */
31
32#ifndef __ARCH_ALPHA_IPR_HH__
33#define __ARCH_ALPHA_IPR_HH__
34
35namespace AlphaISA
36{
37 ////////////////////////////////////////////////////////////////////////
38 //
39 // Internal Processor Reigsters
40 //
41 enum md_ipr_names
42 {
43 RAW_IPR_ISR = 0x100, // interrupt summary register
44 RAW_IPR_ITB_TAG = 0x101, // ITLB tag register
45 RAW_IPR_ITB_PTE = 0x102, // ITLB page table entry register
46 RAW_IPR_ITB_ASN = 0x103, // ITLB address space register
47 RAW_IPR_ITB_PTE_TEMP = 0x104, // ITLB page table entry temp register
48 RAW_IPR_ITB_IA = 0x105, // ITLB invalidate all register
49 RAW_IPR_ITB_IAP = 0x106, // ITLB invalidate all process register
50 RAW_IPR_ITB_IS = 0x107, // ITLB invalidate select register
51 RAW_IPR_SIRR = 0x108, // software interrupt request register
52 RAW_IPR_ASTRR = 0x109, // asynchronous system trap request register
53 RAW_IPR_ASTER = 0x10a, // asynchronous system trap enable register
54 RAW_IPR_EXC_ADDR = 0x10b, // exception address register
55 RAW_IPR_EXC_SUM = 0x10c, // exception summary register
56 RAW_IPR_EXC_MASK = 0x10d, // exception mask register
57 RAW_IPR_PAL_BASE = 0x10e, // PAL base address register
58 RAW_IPR_ICM = 0x10f, // instruction current mode
59 RAW_IPR_IPLR = 0x110, // interrupt priority level register
60 RAW_IPR_INTID = 0x111, // interrupt ID register
61 RAW_IPR_IFAULT_VA_FORM = 0x112, // formatted faulting virtual addr register
62 RAW_IPR_IVPTBR = 0x113, // virtual page table base register
63 RAW_IPR_HWINT_CLR = 0x115, // H/W interrupt clear register
64 RAW_IPR_SL_XMIT = 0x116, // serial line transmit register
65 RAW_IPR_SL_RCV = 0x117, // serial line receive register
66 RAW_IPR_ICSR = 0x118, // instruction control and status register
67 RAW_IPR_IC_FLUSH = 0x119, // instruction cache flush control
68 RAW_IPR_IC_PERR_STAT = 0x11a, // inst cache parity error status register
69 RAW_IPR_PMCTR = 0x11c, // performance counter register
35namespace AlphaISA {
70
36
71 // PAL temporary registers...
72 // register meanings gleaned from osfpal.s source code
73 RAW_IPR_PALtemp0 = 0x140, // local scratch
74 RAW_IPR_PALtemp1 = 0x141, // local scratch
75 RAW_IPR_PALtemp2 = 0x142, // entUna
76 RAW_IPR_PALtemp3 = 0x143, // CPU specific impure area pointer
77 RAW_IPR_PALtemp4 = 0x144, // memory management temp
78 RAW_IPR_PALtemp5 = 0x145, // memory management temp
79 RAW_IPR_PALtemp6 = 0x146, // memory management temp
80 RAW_IPR_PALtemp7 = 0x147, // entIF
81 RAW_IPR_PALtemp8 = 0x148, // intmask
82 RAW_IPR_PALtemp9 = 0x149, // entSys
83 RAW_IPR_PALtemp10 = 0x14a, // ??
84 RAW_IPR_PALtemp11 = 0x14b, // entInt
85 RAW_IPR_PALtemp12 = 0x14c, // entArith
86 RAW_IPR_PALtemp13 = 0x14d, // reserved for platform specific PAL
87 RAW_IPR_PALtemp14 = 0x14e, // reserved for platform specific PAL
88 RAW_IPR_PALtemp15 = 0x14f, // reserved for platform specific PAL
89 RAW_IPR_PALtemp16 = 0x150, // scratch / whami<7:0> / mces<4:0>
90 RAW_IPR_PALtemp17 = 0x151, // sysval
91 RAW_IPR_PALtemp18 = 0x152, // usp
92 RAW_IPR_PALtemp19 = 0x153, // ksp
93 RAW_IPR_PALtemp20 = 0x154, // PTBR
94 RAW_IPR_PALtemp21 = 0x155, // entMM
95 RAW_IPR_PALtemp22 = 0x156, // kgp
96 RAW_IPR_PALtemp23 = 0x157, // PCBB
37////////////////////////////////////////////////////////////////////////
38//
39// Internal Processor Reigsters
40//
41enum md_ipr_names {
42 RAW_IPR_ISR = 0x100, // interrupt summary
43 RAW_IPR_ITB_TAG = 0x101, // ITLB tag
44 RAW_IPR_ITB_PTE = 0x102, // ITLB page table entry
45 RAW_IPR_ITB_ASN = 0x103, // ITLB address space
46 RAW_IPR_ITB_PTE_TEMP = 0x104, // ITLB page table entry temp
47 RAW_IPR_ITB_IA = 0x105, // ITLB invalidate all
48 RAW_IPR_ITB_IAP = 0x106, // ITLB invalidate all process
49 RAW_IPR_ITB_IS = 0x107, // ITLB invalidate select
50 RAW_IPR_SIRR = 0x108, // software interrupt request
51 RAW_IPR_ASTRR = 0x109, // asynchronous system trap request
52 RAW_IPR_ASTER = 0x10a, // asynchronous system trap enable
53 RAW_IPR_EXC_ADDR = 0x10b, // exception address
54 RAW_IPR_EXC_SUM = 0x10c, // exception summary
55 RAW_IPR_EXC_MASK = 0x10d, // exception mask
56 RAW_IPR_PAL_BASE = 0x10e, // PAL base address
57 RAW_IPR_ICM = 0x10f, // instruction current mode
58 RAW_IPR_IPLR = 0x110, // interrupt priority level
59 RAW_IPR_INTID = 0x111, // interrupt ID
60 RAW_IPR_IFAULT_VA_FORM = 0x112, // formatted faulting virtual addr
61 RAW_IPR_IVPTBR = 0x113, // virtual page table base
62 RAW_IPR_HWINT_CLR = 0x115, // H/W interrupt clear
63 RAW_IPR_SL_XMIT = 0x116, // serial line transmit
64 RAW_IPR_SL_RCV = 0x117, // serial line receive
65 RAW_IPR_ICSR = 0x118, // instruction control and status
66 RAW_IPR_IC_FLUSH = 0x119, // instruction cache flush control
67 RAW_IPR_IC_PERR_STAT = 0x11a, // inst cache parity error status
68 RAW_IPR_PMCTR = 0x11c, // performance counter
97
69
98 RAW_IPR_DTB_ASN = 0x200, // DTLB address space number register
99 RAW_IPR_DTB_CM = 0x201, // DTLB current mode register
100 RAW_IPR_DTB_TAG = 0x202, // DTLB tag register
101 RAW_IPR_DTB_PTE = 0x203, // DTLB page table entry register
102 RAW_IPR_DTB_PTE_TEMP = 0x204, // DTLB page table entry temporary register
70 // PAL temporary registers...
71 // register meanings gleaned from osfpal.s source code
72 RAW_IPR_PALtemp0 = 0x140, // local scratch
73 RAW_IPR_PALtemp1 = 0x141, // local scratch
74 RAW_IPR_PALtemp2 = 0x142, // entUna
75 RAW_IPR_PALtemp3 = 0x143, // CPU specific impure area pointer
76 RAW_IPR_PALtemp4 = 0x144, // memory management temp
77 RAW_IPR_PALtemp5 = 0x145, // memory management temp
78 RAW_IPR_PALtemp6 = 0x146, // memory management temp
79 RAW_IPR_PALtemp7 = 0x147, // entIF
80 RAW_IPR_PALtemp8 = 0x148, // intmask
81 RAW_IPR_PALtemp9 = 0x149, // entSys
82 RAW_IPR_PALtemp10 = 0x14a, // ??
83 RAW_IPR_PALtemp11 = 0x14b, // entInt
84 RAW_IPR_PALtemp12 = 0x14c, // entArith
85 RAW_IPR_PALtemp13 = 0x14d, // reserved for platform specific PAL
86 RAW_IPR_PALtemp14 = 0x14e, // reserved for platform specific PAL
87 RAW_IPR_PALtemp15 = 0x14f, // reserved for platform specific PAL
88 RAW_IPR_PALtemp16 = 0x150, // scratch / whami<7:0> / mces<4:0>
89 RAW_IPR_PALtemp17 = 0x151, // sysval
90 RAW_IPR_PALtemp18 = 0x152, // usp
91 RAW_IPR_PALtemp19 = 0x153, // ksp
92 RAW_IPR_PALtemp20 = 0x154, // PTBR
93 RAW_IPR_PALtemp21 = 0x155, // entMM
94 RAW_IPR_PALtemp22 = 0x156, // kgp
95 RAW_IPR_PALtemp23 = 0x157, // PCBB
103
96
104 RAW_IPR_MM_STAT = 0x205, // data MMU fault status register
105 RAW_IPR_VA = 0x206, // fault virtual address register
106 RAW_IPR_VA_FORM = 0x207, // formatted virtual address register
107 RAW_IPR_MVPTBR = 0x208, // MTU virtual page table base register
108 RAW_IPR_DTB_IAP = 0x209, // DTLB invalidate all process register
109 RAW_IPR_DTB_IA = 0x20a, // DTLB invalidate all register
110 RAW_IPR_DTB_IS = 0x20b, // DTLB invalidate single register
111 RAW_IPR_ALT_MODE = 0x20c, // alternate mode register
112 RAW_IPR_CC = 0x20d, // cycle counter register
113 RAW_IPR_CC_CTL = 0x20e, // cycle counter control register
114 RAW_IPR_MCSR = 0x20f, // MTU control register
97 RAW_IPR_DTB_ASN = 0x200, // DTLB address space number
98 RAW_IPR_DTB_CM = 0x201, // DTLB current mode
99 RAW_IPR_DTB_TAG = 0x202, // DTLB tag
100 RAW_IPR_DTB_PTE = 0x203, // DTLB page table entry
101 RAW_IPR_DTB_PTE_TEMP = 0x204, // DTLB page table entry temporary
115
102
116 RAW_IPR_DC_FLUSH = 0x210,
117 RAW_IPR_DC_PERR_STAT = 0x212, // Dcache parity error status register
118 RAW_IPR_DC_TEST_CTL = 0x213, // Dcache test tag control register
119 RAW_IPR_DC_TEST_TAG = 0x214, // Dcache test tag register
120 RAW_IPR_DC_TEST_TAG_TEMP = 0x215, // Dcache test tag temporary register
121 RAW_IPR_DC_MODE = 0x216, // Dcache mode register
122 RAW_IPR_MAF_MODE = 0x217, // miss address file mode register
103 RAW_IPR_MM_STAT = 0x205, // data MMU fault status
104 RAW_IPR_VA = 0x206, // fault virtual address
105 RAW_IPR_VA_FORM = 0x207, // formatted virtual address
106 RAW_IPR_MVPTBR = 0x208, // MTU virtual page table base
107 RAW_IPR_DTB_IAP = 0x209, // DTLB invalidate all process
108 RAW_IPR_DTB_IA = 0x20a, // DTLB invalidate all
109 RAW_IPR_DTB_IS = 0x20b, // DTLB invalidate single
110 RAW_IPR_ALT_MODE = 0x20c, // alternate mode
111 RAW_IPR_CC = 0x20d, // cycle counter
112 RAW_IPR_CC_CTL = 0x20e, // cycle counter control
113 RAW_IPR_MCSR = 0x20f, // MTU control
123
114
124 MaxInternalProcRegs // number of IPR registers
125 };
115 RAW_IPR_DC_FLUSH = 0x210,
116 RAW_IPR_DC_PERR_STAT = 0x212, // Dcache parity error status
117 RAW_IPR_DC_TEST_CTL = 0x213, // Dcache test tag control
118 RAW_IPR_DC_TEST_TAG = 0x214, // Dcache test tag
119 RAW_IPR_DC_TEST_TAG_TEMP = 0x215, // Dcache test tag temporary
120 RAW_IPR_DC_MODE = 0x216, // Dcache mode
121 RAW_IPR_MAF_MODE = 0x217, // miss address file mode
126
122
127 enum MiscRegIpr
128 {
129 //Write only
130 MinWriteOnlyIpr,
131 IPR_HWINT_CLR = MinWriteOnlyIpr,
132 IPR_SL_XMIT,
133 IPR_DC_FLUSH,
134 IPR_IC_FLUSH,
135 IPR_ALT_MODE,
136 IPR_DTB_IA,
137 IPR_DTB_IAP,
138 IPR_ITB_IA,
139 MaxWriteOnlyIpr,
140 IPR_ITB_IAP = MaxWriteOnlyIpr,
123 MaxInternalProcRegs // number of IPRs
124};
141
125
142 //Read only
143 MinReadOnlyIpr,
144 IPR_INTID = MinReadOnlyIpr,
145 IPR_SL_RCV,
146 IPR_MM_STAT,
147 IPR_ITB_PTE_TEMP,
148 MaxReadOnlyIpr,
149 IPR_DTB_PTE_TEMP = MaxReadOnlyIpr,
126enum MiscRegIpr
127{
128 //Write only
129 MinWriteOnlyIpr,
130 IPR_HWINT_CLR = MinWriteOnlyIpr,
131 IPR_SL_XMIT,
132 IPR_DC_FLUSH,
133 IPR_IC_FLUSH,
134 IPR_ALT_MODE,
135 IPR_DTB_IA,
136 IPR_DTB_IAP,
137 IPR_ITB_IA,
138 MaxWriteOnlyIpr,
139 IPR_ITB_IAP = MaxWriteOnlyIpr,
150
140
151 IPR_ISR,
152 IPR_ITB_TAG,
153 IPR_ITB_PTE,
154 IPR_ITB_ASN,
155 IPR_ITB_IS,
156 IPR_SIRR,
157 IPR_ASTRR,
158 IPR_ASTER,
159 IPR_EXC_ADDR,
160 IPR_EXC_SUM,
161 IPR_EXC_MASK,
162 IPR_PAL_BASE,
163 IPR_ICM,
164 IPR_IPLR,
165 IPR_IFAULT_VA_FORM,
166 IPR_IVPTBR,
167 IPR_ICSR,
168 IPR_IC_PERR_STAT,
169 IPR_PMCTR,
141 //Read only
142 MinReadOnlyIpr,
143 IPR_INTID = MinReadOnlyIpr,
144 IPR_SL_RCV,
145 IPR_MM_STAT,
146 IPR_ITB_PTE_TEMP,
147 MaxReadOnlyIpr,
148 IPR_DTB_PTE_TEMP = MaxReadOnlyIpr,
170
149
171 // PAL temporary registers...
172 // register meanings gleaned from osfpal.s source code
173 IPR_PALtemp0,
174 IPR_PALtemp1,
175 IPR_PALtemp2,
176 IPR_PALtemp3,
177 IPR_PALtemp4,
178 IPR_PALtemp5,
179 IPR_PALtemp6,
180 IPR_PALtemp7,
181 IPR_PALtemp8,
182 IPR_PALtemp9,
183 IPR_PALtemp10,
184 IPR_PALtemp11,
185 IPR_PALtemp12,
186 IPR_PALtemp13,
187 IPR_PALtemp14,
188 IPR_PALtemp15,
189 IPR_PALtemp16,
190 IPR_PALtemp17,
191 IPR_PALtemp18,
192 IPR_PALtemp19,
193 IPR_PALtemp20,
194 IPR_PALtemp21,
195 IPR_PALtemp22,
196 IPR_PALtemp23,
150 IPR_ISR,
151 IPR_ITB_TAG,
152 IPR_ITB_PTE,
153 IPR_ITB_ASN,
154 IPR_ITB_IS,
155 IPR_SIRR,
156 IPR_ASTRR,
157 IPR_ASTER,
158 IPR_EXC_ADDR,
159 IPR_EXC_SUM,
160 IPR_EXC_MASK,
161 IPR_PAL_BASE,
162 IPR_ICM,
163 IPR_IPLR,
164 IPR_IFAULT_VA_FORM,
165 IPR_IVPTBR,
166 IPR_ICSR,
167 IPR_IC_PERR_STAT,
168 IPR_PMCTR,
197
169
198 IPR_DTB_ASN,
199 IPR_DTB_CM,
200 IPR_DTB_TAG,
201 IPR_DTB_PTE,
170 // PAL temporary registers...
171 // register meanings gleaned from osfpal.s source code
172 IPR_PALtemp0,
173 IPR_PALtemp1,
174 IPR_PALtemp2,
175 IPR_PALtemp3,
176 IPR_PALtemp4,
177 IPR_PALtemp5,
178 IPR_PALtemp6,
179 IPR_PALtemp7,
180 IPR_PALtemp8,
181 IPR_PALtemp9,
182 IPR_PALtemp10,
183 IPR_PALtemp11,
184 IPR_PALtemp12,
185 IPR_PALtemp13,
186 IPR_PALtemp14,
187 IPR_PALtemp15,
188 IPR_PALtemp16,
189 IPR_PALtemp17,
190 IPR_PALtemp18,
191 IPR_PALtemp19,
192 IPR_PALtemp20,
193 IPR_PALtemp21,
194 IPR_PALtemp22,
195 IPR_PALtemp23,
202
196
203 IPR_VA,
204 IPR_VA_FORM,
205 IPR_MVPTBR,
206 IPR_DTB_IS,
207 IPR_CC,
208 IPR_CC_CTL,
209 IPR_MCSR,
197 IPR_DTB_ASN,
198 IPR_DTB_CM,
199 IPR_DTB_TAG,
200 IPR_DTB_PTE,
210
201
211 IPR_DC_PERR_STAT,
212 IPR_DC_TEST_CTL,
213 IPR_DC_TEST_TAG,
214 IPR_DC_TEST_TAG_TEMP,
215 IPR_DC_MODE,
216 IPR_MAF_MODE,
202 IPR_VA,
203 IPR_VA_FORM,
204 IPR_MVPTBR,
205 IPR_DTB_IS,
206 IPR_CC,
207 IPR_CC_CTL,
208 IPR_MCSR,
217
209
218 NumInternalProcRegs // number of IPR registers
219 };
210 IPR_DC_PERR_STAT,
211 IPR_DC_TEST_CTL,
212 IPR_DC_TEST_TAG,
213 IPR_DC_TEST_TAG_TEMP,
214 IPR_DC_MODE,
215 IPR_MAF_MODE,
220
216
221 inline bool IprIsWritable(int index)
222 {
223 return index < MinReadOnlyIpr || index > MaxReadOnlyIpr;
224 }
217 NumInternalProcRegs // number of IPR registers
218};
225
219
226 inline bool IprIsReadable(int index)
227 {
228 return index < MinWriteOnlyIpr || index > MaxWriteOnlyIpr;
229 }
220inline bool
221IprIsWritable(int index)
222{
223 return index < MinReadOnlyIpr || index > MaxReadOnlyIpr;
224}
230
225
231 extern md_ipr_names MiscRegIndexToIpr[NumInternalProcRegs];
232 extern int IprToMiscRegIndex[MaxInternalProcRegs];
233
234 void initializeIprTable();
226inline bool
227IprIsReadable(int index)
228{
229 return index < MinWriteOnlyIpr || index > MaxWriteOnlyIpr;
235}
236
230}
231
237#endif
232extern md_ipr_names MiscRegIndexToIpr[NumInternalProcRegs];
233extern int IprToMiscRegIndex[MaxInternalProcRegs];
234
235void initializeIprTable();
236
237} // namespace AlphaISA
238
239#endif // __ARCH_ALPHA_IPR_HH__