1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
--- 26 unchanged lines hidden (view full) ---
35namespace AlphaISA
36{
37 ////////////////////////////////////////////////////////////////////////
38 //
39 // Internal Processor Reigsters
40 //
41 enum md_ipr_names
42 {
43 IPR_ISR = 0x100, // interrupt summary register
44 IPR_ITB_TAG = 0x101, // ITLB tag register
45 IPR_ITB_PTE = 0x102, // ITLB page table entry register
46 IPR_ITB_ASN = 0x103, // ITLB address space register
47 IPR_ITB_PTE_TEMP = 0x104, // ITLB page table entry temp register
48 IPR_ITB_IA = 0x105, // ITLB invalidate all register
49 IPR_ITB_IAP = 0x106, // ITLB invalidate all process register
50 IPR_ITB_IS = 0x107, // ITLB invalidate select register
51 IPR_SIRR = 0x108, // software interrupt request register
52 IPR_ASTRR = 0x109, // asynchronous system trap request register
53 IPR_ASTER = 0x10a, // asynchronous system trap enable register
54 IPR_EXC_ADDR = 0x10b, // exception address register
55 IPR_EXC_SUM = 0x10c, // exception summary register
56 IPR_EXC_MASK = 0x10d, // exception mask register
57 IPR_PAL_BASE = 0x10e, // PAL base address register
58 IPR_ICM = 0x10f, // instruction current mode
59 IPR_IPLR = 0x110, // interrupt priority level register
60 IPR_INTID = 0x111, // interrupt ID register
61 IPR_IFAULT_VA_FORM = 0x112, // formatted faulting virtual addr register
62 IPR_IVPTBR = 0x113, // virtual page table base register
63 IPR_HWINT_CLR = 0x115, // H/W interrupt clear register
64 IPR_SL_XMIT = 0x116, // serial line transmit register
65 IPR_SL_RCV = 0x117, // serial line receive register
66 IPR_ICSR = 0x118, // instruction control and status register
67 IPR_IC_FLUSH = 0x119, // instruction cache flush control
68 IPR_IC_PERR_STAT = 0x11a, // inst cache parity error status register
69 IPR_PMCTR = 0x11c, // performance counter register
70
71 // PAL temporary registers...
72 // register meanings gleaned from osfpal.s source code
73 IPR_PALtemp0 = 0x140, // local scratch
74 IPR_PALtemp1 = 0x141, // local scratch
75 IPR_PALtemp2 = 0x142, // entUna
76 IPR_PALtemp3 = 0x143, // CPU specific impure area pointer
77 IPR_PALtemp4 = 0x144, // memory management temp
78 IPR_PALtemp5 = 0x145, // memory management temp
79 IPR_PALtemp6 = 0x146, // memory management temp
80 IPR_PALtemp7 = 0x147, // entIF
81 IPR_PALtemp8 = 0x148, // intmask
82 IPR_PALtemp9 = 0x149, // entSys
83 IPR_PALtemp10 = 0x14a, // ??
84 IPR_PALtemp11 = 0x14b, // entInt
85 IPR_PALtemp12 = 0x14c, // entArith
86 IPR_PALtemp13 = 0x14d, // reserved for platform specific PAL
87 IPR_PALtemp14 = 0x14e, // reserved for platform specific PAL
88 IPR_PALtemp15 = 0x14f, // reserved for platform specific PAL
89 IPR_PALtemp16 = 0x150, // scratch / whami<7:0> / mces<4:0>
90 IPR_PALtemp17 = 0x151, // sysval
91 IPR_PALtemp18 = 0x152, // usp
92 IPR_PALtemp19 = 0x153, // ksp
93 IPR_PALtemp20 = 0x154, // PTBR
94 IPR_PALtemp21 = 0x155, // entMM
95 IPR_PALtemp22 = 0x156, // kgp
96 IPR_PALtemp23 = 0x157, // PCBB
97
98 IPR_DTB_ASN = 0x200, // DTLB address space number register
99 IPR_DTB_CM = 0x201, // DTLB current mode register
100 IPR_DTB_TAG = 0x202, // DTLB tag register
101 IPR_DTB_PTE = 0x203, // DTLB page table entry register
102 IPR_DTB_PTE_TEMP = 0x204, // DTLB page table entry temporary register
103
104 IPR_MM_STAT = 0x205, // data MMU fault status register
105 IPR_VA = 0x206, // fault virtual address register
106 IPR_VA_FORM = 0x207, // formatted virtual address register
107 IPR_MVPTBR = 0x208, // MTU virtual page table base register
108 IPR_DTB_IAP = 0x209, // DTLB invalidate all process register
109 IPR_DTB_IA = 0x20a, // DTLB invalidate all register
110 IPR_DTB_IS = 0x20b, // DTLB invalidate single register
111 IPR_ALT_MODE = 0x20c, // alternate mode register
112 IPR_CC = 0x20d, // cycle counter register
113 IPR_CC_CTL = 0x20e, // cycle counter control register
114 IPR_MCSR = 0x20f, // MTU control register
115
116 IPR_DC_FLUSH = 0x210,
117 IPR_DC_PERR_STAT = 0x212, // Dcache parity error status register
118 IPR_DC_TEST_CTL = 0x213, // Dcache test tag control register
119 IPR_DC_TEST_TAG = 0x214, // Dcache test tag register
120 IPR_DC_TEST_TAG_TEMP = 0x215, // Dcache test tag temporary register
121 IPR_DC_MODE = 0x216, // Dcache mode register
122 IPR_MAF_MODE = 0x217, // miss address file mode register
123
124 MaxInternalProcRegs // number of IPR registers
125 };
126
127 enum MiscRegIpr
128 {
129 //Write only
130 MinWriteOnlyIpr,
131 MISCREG_IPR_HWINT_CLR = MinWriteOnlyIpr,
132 MISCREG_IPR_SL_XMIT,
133 MISCREG_IPR_DC_FLUSH,
134 MISCREG_IPR_IC_FLUSH,
135 MISCREG_IPR_ALT_MODE,
136 MISCREG_IPR_DTB_IA,
137 MISCREG_IPR_DTB_IAP,
138 MISCREG_IPR_ITB_IA,
139 MaxWriteOnlyIpr,
140 MISCREG_IPR_ITB_IAP = MaxWriteOnlyIpr,
141
142 //Read only
143 MinReadOnlyIpr,
144 MISCREG_IPR_INTID = MinReadOnlyIpr,
145 MISCREG_IPR_SL_RCV,
146 MISCREG_IPR_MM_STAT,
147 MISCREG_IPR_ITB_PTE_TEMP,
148 MaxReadOnlyIpr,
149 MISCREG_IPR_DTB_PTE_TEMP = MaxReadOnlyIpr,
150
151 MISCREG_IPR_ISR,
152 MISCREG_IPR_ITB_TAG,
153 MISCREG_IPR_ITB_PTE,
154 MISCREG_IPR_ITB_ASN,
155 MISCREG_IPR_ITB_IS,
156 MISCREG_IPR_SIRR,
157 MISCREG_IPR_ASTRR,
158 MISCREG_IPR_ASTER,
159 MISCREG_IPR_EXC_ADDR,
160 MISCREG_IPR_EXC_SUM,
161 MISCREG_IPR_EXC_MASK,
162 MISCREG_IPR_PAL_BASE,
163 MISCREG_IPR_ICM,
164 MISCREG_IPR_IPLR,
165 MISCREG_IPR_IFAULT_VA_FORM,
166 MISCREG_IPR_IVPTBR,
167 MISCREG_IPR_ICSR,
168 MISCREG_IPR_IC_PERR_STAT,
169 MISCREG_IPR_PMCTR,
170
171 // PAL temporary registers...
172 // register meanings gleaned from osfpal.s source code
173 MISCREG_IPR_PALtemp0,
174 MISCREG_IPR_PALtemp1,
175 MISCREG_IPR_PALtemp2,
176 MISCREG_IPR_PALtemp3,
177 MISCREG_IPR_PALtemp4,
178 MISCREG_IPR_PALtemp5,
179 MISCREG_IPR_PALtemp6,
180 MISCREG_IPR_PALtemp7,
181 MISCREG_IPR_PALtemp8,
182 MISCREG_IPR_PALtemp9,
183 MISCREG_IPR_PALtemp10,
184 MISCREG_IPR_PALtemp11,
185 MISCREG_IPR_PALtemp12,
186 MISCREG_IPR_PALtemp13,
187 MISCREG_IPR_PALtemp14,
188 MISCREG_IPR_PALtemp15,
189 MISCREG_IPR_PALtemp16,
190 MISCREG_IPR_PALtemp17,
191 MISCREG_IPR_PALtemp18,
192 MISCREG_IPR_PALtemp19,
193 MISCREG_IPR_PALtemp20,
194 MISCREG_IPR_PALtemp21,
195 MISCREG_IPR_PALtemp22,
196 MISCREG_IPR_PALtemp23,
197
198 MISCREG_IPR_DTB_ASN,
199 MISCREG_IPR_DTB_CM,
200 MISCREG_IPR_DTB_TAG,
201 MISCREG_IPR_DTB_PTE,
202
203 MISCREG_IPR_VA,
204 MISCREG_IPR_VA_FORM,
205 MISCREG_IPR_MVPTBR,
206 MISCREG_IPR_DTB_IS,
207 MISCREG_IPR_CC,
208 MISCREG_IPR_CC_CTL,
209 MISCREG_IPR_MCSR,
210
211 MISCREG_IPR_DC_PERR_STAT,
212 MISCREG_IPR_DC_TEST_CTL,
213 MISCREG_IPR_DC_TEST_TAG,
214 MISCREG_IPR_DC_TEST_TAG_TEMP,
215 MISCREG_IPR_DC_MODE,
216 MISCREG_IPR_MAF_MODE,
217
218 NumInternalProcRegs // number of IPR registers
219 };
220
221
222 extern md_ipr_names MiscRegIndexToIpr[NumInternalProcRegs];
223 extern int IprToMiscRegIndex[MaxInternalProcRegs];
224
225 void initializeIprTable();
226}
227
228#endif
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
--- 26 unchanged lines hidden (view full) ---
35namespace AlphaISA
36{
37 ////////////////////////////////////////////////////////////////////////
38 //
39 // Internal Processor Reigsters
40 //
41 enum md_ipr_names
42 {
43 IPR_ISR = 0x100, // interrupt summary register
44 IPR_ITB_TAG = 0x101, // ITLB tag register
45 IPR_ITB_PTE = 0x102, // ITLB page table entry register
46 IPR_ITB_ASN = 0x103, // ITLB address space register
47 IPR_ITB_PTE_TEMP = 0x104, // ITLB page table entry temp register
48 IPR_ITB_IA = 0x105, // ITLB invalidate all register
49 IPR_ITB_IAP = 0x106, // ITLB invalidate all process register
50 IPR_ITB_IS = 0x107, // ITLB invalidate select register
51 IPR_SIRR = 0x108, // software interrupt request register
52 IPR_ASTRR = 0x109, // asynchronous system trap request register
53 IPR_ASTER = 0x10a, // asynchronous system trap enable register
54 IPR_EXC_ADDR = 0x10b, // exception address register
55 IPR_EXC_SUM = 0x10c, // exception summary register
56 IPR_EXC_MASK = 0x10d, // exception mask register
57 IPR_PAL_BASE = 0x10e, // PAL base address register
58 IPR_ICM = 0x10f, // instruction current mode
59 IPR_IPLR = 0x110, // interrupt priority level register
60 IPR_INTID = 0x111, // interrupt ID register
61 IPR_IFAULT_VA_FORM = 0x112, // formatted faulting virtual addr register
62 IPR_IVPTBR = 0x113, // virtual page table base register
63 IPR_HWINT_CLR = 0x115, // H/W interrupt clear register
64 IPR_SL_XMIT = 0x116, // serial line transmit register
65 IPR_SL_RCV = 0x117, // serial line receive register
66 IPR_ICSR = 0x118, // instruction control and status register
67 IPR_IC_FLUSH = 0x119, // instruction cache flush control
68 IPR_IC_PERR_STAT = 0x11a, // inst cache parity error status register
69 IPR_PMCTR = 0x11c, // performance counter register
70
71 // PAL temporary registers...
72 // register meanings gleaned from osfpal.s source code
73 IPR_PALtemp0 = 0x140, // local scratch
74 IPR_PALtemp1 = 0x141, // local scratch
75 IPR_PALtemp2 = 0x142, // entUna
76 IPR_PALtemp3 = 0x143, // CPU specific impure area pointer
77 IPR_PALtemp4 = 0x144, // memory management temp
78 IPR_PALtemp5 = 0x145, // memory management temp
79 IPR_PALtemp6 = 0x146, // memory management temp
80 IPR_PALtemp7 = 0x147, // entIF
81 IPR_PALtemp8 = 0x148, // intmask
82 IPR_PALtemp9 = 0x149, // entSys
83 IPR_PALtemp10 = 0x14a, // ??
84 IPR_PALtemp11 = 0x14b, // entInt
85 IPR_PALtemp12 = 0x14c, // entArith
86 IPR_PALtemp13 = 0x14d, // reserved for platform specific PAL
87 IPR_PALtemp14 = 0x14e, // reserved for platform specific PAL
88 IPR_PALtemp15 = 0x14f, // reserved for platform specific PAL
89 IPR_PALtemp16 = 0x150, // scratch / whami<7:0> / mces<4:0>
90 IPR_PALtemp17 = 0x151, // sysval
91 IPR_PALtemp18 = 0x152, // usp
92 IPR_PALtemp19 = 0x153, // ksp
93 IPR_PALtemp20 = 0x154, // PTBR
94 IPR_PALtemp21 = 0x155, // entMM
95 IPR_PALtemp22 = 0x156, // kgp
96 IPR_PALtemp23 = 0x157, // PCBB
97
98 IPR_DTB_ASN = 0x200, // DTLB address space number register
99 IPR_DTB_CM = 0x201, // DTLB current mode register
100 IPR_DTB_TAG = 0x202, // DTLB tag register
101 IPR_DTB_PTE = 0x203, // DTLB page table entry register
102 IPR_DTB_PTE_TEMP = 0x204, // DTLB page table entry temporary register
103
104 IPR_MM_STAT = 0x205, // data MMU fault status register
105 IPR_VA = 0x206, // fault virtual address register
106 IPR_VA_FORM = 0x207, // formatted virtual address register
107 IPR_MVPTBR = 0x208, // MTU virtual page table base register
108 IPR_DTB_IAP = 0x209, // DTLB invalidate all process register
109 IPR_DTB_IA = 0x20a, // DTLB invalidate all register
110 IPR_DTB_IS = 0x20b, // DTLB invalidate single register
111 IPR_ALT_MODE = 0x20c, // alternate mode register
112 IPR_CC = 0x20d, // cycle counter register
113 IPR_CC_CTL = 0x20e, // cycle counter control register
114 IPR_MCSR = 0x20f, // MTU control register
115
116 IPR_DC_FLUSH = 0x210,
117 IPR_DC_PERR_STAT = 0x212, // Dcache parity error status register
118 IPR_DC_TEST_CTL = 0x213, // Dcache test tag control register
119 IPR_DC_TEST_TAG = 0x214, // Dcache test tag register
120 IPR_DC_TEST_TAG_TEMP = 0x215, // Dcache test tag temporary register
121 IPR_DC_MODE = 0x216, // Dcache mode register
122 IPR_MAF_MODE = 0x217, // miss address file mode register
123
124 MaxInternalProcRegs // number of IPR registers
125 };
126
127 enum MiscRegIpr
128 {
129 //Write only
130 MinWriteOnlyIpr,
131 MISCREG_IPR_HWINT_CLR = MinWriteOnlyIpr,
132 MISCREG_IPR_SL_XMIT,
133 MISCREG_IPR_DC_FLUSH,
134 MISCREG_IPR_IC_FLUSH,
135 MISCREG_IPR_ALT_MODE,
136 MISCREG_IPR_DTB_IA,
137 MISCREG_IPR_DTB_IAP,
138 MISCREG_IPR_ITB_IA,
139 MaxWriteOnlyIpr,
140 MISCREG_IPR_ITB_IAP = MaxWriteOnlyIpr,
141
142 //Read only
143 MinReadOnlyIpr,
144 MISCREG_IPR_INTID = MinReadOnlyIpr,
145 MISCREG_IPR_SL_RCV,
146 MISCREG_IPR_MM_STAT,
147 MISCREG_IPR_ITB_PTE_TEMP,
148 MaxReadOnlyIpr,
149 MISCREG_IPR_DTB_PTE_TEMP = MaxReadOnlyIpr,
150
151 MISCREG_IPR_ISR,
152 MISCREG_IPR_ITB_TAG,
153 MISCREG_IPR_ITB_PTE,
154 MISCREG_IPR_ITB_ASN,
155 MISCREG_IPR_ITB_IS,
156 MISCREG_IPR_SIRR,
157 MISCREG_IPR_ASTRR,
158 MISCREG_IPR_ASTER,
159 MISCREG_IPR_EXC_ADDR,
160 MISCREG_IPR_EXC_SUM,
161 MISCREG_IPR_EXC_MASK,
162 MISCREG_IPR_PAL_BASE,
163 MISCREG_IPR_ICM,
164 MISCREG_IPR_IPLR,
165 MISCREG_IPR_IFAULT_VA_FORM,
166 MISCREG_IPR_IVPTBR,
167 MISCREG_IPR_ICSR,
168 MISCREG_IPR_IC_PERR_STAT,
169 MISCREG_IPR_PMCTR,
170
171 // PAL temporary registers...
172 // register meanings gleaned from osfpal.s source code
173 MISCREG_IPR_PALtemp0,
174 MISCREG_IPR_PALtemp1,
175 MISCREG_IPR_PALtemp2,
176 MISCREG_IPR_PALtemp3,
177 MISCREG_IPR_PALtemp4,
178 MISCREG_IPR_PALtemp5,
179 MISCREG_IPR_PALtemp6,
180 MISCREG_IPR_PALtemp7,
181 MISCREG_IPR_PALtemp8,
182 MISCREG_IPR_PALtemp9,
183 MISCREG_IPR_PALtemp10,
184 MISCREG_IPR_PALtemp11,
185 MISCREG_IPR_PALtemp12,
186 MISCREG_IPR_PALtemp13,
187 MISCREG_IPR_PALtemp14,
188 MISCREG_IPR_PALtemp15,
189 MISCREG_IPR_PALtemp16,
190 MISCREG_IPR_PALtemp17,
191 MISCREG_IPR_PALtemp18,
192 MISCREG_IPR_PALtemp19,
193 MISCREG_IPR_PALtemp20,
194 MISCREG_IPR_PALtemp21,
195 MISCREG_IPR_PALtemp22,
196 MISCREG_IPR_PALtemp23,
197
198 MISCREG_IPR_DTB_ASN,
199 MISCREG_IPR_DTB_CM,
200 MISCREG_IPR_DTB_TAG,
201 MISCREG_IPR_DTB_PTE,
202
203 MISCREG_IPR_VA,
204 MISCREG_IPR_VA_FORM,
205 MISCREG_IPR_MVPTBR,
206 MISCREG_IPR_DTB_IS,
207 MISCREG_IPR_CC,
208 MISCREG_IPR_CC_CTL,
209 MISCREG_IPR_MCSR,
210
211 MISCREG_IPR_DC_PERR_STAT,
212 MISCREG_IPR_DC_TEST_CTL,
213 MISCREG_IPR_DC_TEST_TAG,
214 MISCREG_IPR_DC_TEST_TAG_TEMP,
215 MISCREG_IPR_DC_MODE,
216 MISCREG_IPR_MAF_MODE,
217
218 NumInternalProcRegs // number of IPR registers
219 };
220
221
222 extern md_ipr_names MiscRegIndexToIpr[NumInternalProcRegs];
223 extern int IprToMiscRegIndex[MaxInternalProcRegs];
224
225 void initializeIprTable();
226}
227
228#endif