| ipr.cc (3459:dd091092c8bb) | ipr.cc (5543:3af77710f397) |
|---|---|
| 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 24 unchanged lines hidden (view full) --- 33 34#include "arch/alpha/ipr.hh" 35 36namespace AlphaISA 37{ 38 md_ipr_names MiscRegIndexToIpr[NumInternalProcRegs] = 39 { 40 //Write only | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 24 unchanged lines hidden (view full) --- 33 34#include "arch/alpha/ipr.hh" 35 36namespace AlphaISA 37{ 38 md_ipr_names MiscRegIndexToIpr[NumInternalProcRegs] = 39 { 40 //Write only |
| 41 RAW_IPR_HWINT_CLR, // H/W interrupt clear register 42 RAW_IPR_SL_XMIT, // serial line transmit register | 41 RAW_IPR_HWINT_CLR, // H/W interrupt clear register 42 RAW_IPR_SL_XMIT, // serial line transmit register |
| 43 RAW_IPR_DC_FLUSH, | 43 RAW_IPR_DC_FLUSH, |
| 44 RAW_IPR_IC_FLUSH, // instruction cache flush control 45 RAW_IPR_ALT_MODE, // alternate mode register 46 RAW_IPR_DTB_IA, // DTLB invalidate all register 47 RAW_IPR_DTB_IAP, // DTLB invalidate all process register 48 RAW_IPR_ITB_IA, // ITLB invalidate all register 49 RAW_IPR_ITB_IAP, // ITLB invalidate all process register | 44 RAW_IPR_IC_FLUSH, // instruction cache flush control 45 RAW_IPR_ALT_MODE, // alternate mode register 46 RAW_IPR_DTB_IA, // DTLB invalidate all register 47 RAW_IPR_DTB_IAP, // DTLB invalidate all process register 48 RAW_IPR_ITB_IA, // ITLB invalidate all register 49 RAW_IPR_ITB_IAP, // ITLB invalidate all process register |
| 50 51 //Read only | 50 51 //Read only |
| 52 RAW_IPR_INTID, // interrupt ID register 53 RAW_IPR_SL_RCV, // serial line receive register 54 RAW_IPR_MM_STAT, // data MMU fault status register 55 RAW_IPR_ITB_PTE_TEMP, // ITLB page table entry temp register 56 RAW_IPR_DTB_PTE_TEMP, // DTLB page table entry temporary register | 52 RAW_IPR_INTID, // interrupt ID register 53 RAW_IPR_SL_RCV, // serial line receive register 54 RAW_IPR_MM_STAT, // data MMU fault status register 55 RAW_IPR_ITB_PTE_TEMP, // ITLB page table entry temp register 56 RAW_IPR_DTB_PTE_TEMP, // DTLB page table entry temporary register |
| 57 | 57 |
| 58 RAW_IPR_ISR, // interrupt summary register 59 RAW_IPR_ITB_TAG, // ITLB tag register 60 RAW_IPR_ITB_PTE, // ITLB page table entry register 61 RAW_IPR_ITB_ASN, // ITLB address space register 62 RAW_IPR_ITB_IS, // ITLB invalidate select register 63 RAW_IPR_SIRR, // software interrupt request register 64 RAW_IPR_ASTRR, // asynchronous system trap request register 65 RAW_IPR_ASTER, // asynchronous system trap enable register 66 RAW_IPR_EXC_ADDR, // exception address register 67 RAW_IPR_EXC_SUM, // exception summary register 68 RAW_IPR_EXC_MASK, // exception mask register 69 RAW_IPR_PAL_BASE, // PAL base address register 70 RAW_IPR_ICM, // instruction current mode 71 RAW_IPR_IPLR, // interrupt priority level register 72 RAW_IPR_IFAULT_VA_FORM, // formatted faulting virtual addr register 73 RAW_IPR_IVPTBR, // virtual page table base register 74 RAW_IPR_ICSR, // instruction control and status register 75 RAW_IPR_IC_PERR_STAT, // inst cache parity error status register 76 RAW_IPR_PMCTR, // performance counter register | 58 RAW_IPR_ISR, // interrupt summary register 59 RAW_IPR_ITB_TAG, // ITLB tag register 60 RAW_IPR_ITB_PTE, // ITLB page table entry register 61 RAW_IPR_ITB_ASN, // ITLB address space register 62 RAW_IPR_ITB_IS, // ITLB invalidate select register 63 RAW_IPR_SIRR, // software interrupt request register 64 RAW_IPR_ASTRR, // asynchronous system trap request register 65 RAW_IPR_ASTER, // asynchronous system trap enable register 66 RAW_IPR_EXC_ADDR, // exception address register 67 RAW_IPR_EXC_SUM, // exception summary register 68 RAW_IPR_EXC_MASK, // exception mask register 69 RAW_IPR_PAL_BASE, // PAL base address register 70 RAW_IPR_ICM, // instruction current mode 71 RAW_IPR_IPLR, // interrupt priority level register 72 RAW_IPR_IFAULT_VA_FORM, // formatted faulting virtual addr register 73 RAW_IPR_IVPTBR, // virtual page table base register 74 RAW_IPR_ICSR, // instruction control and status register 75 RAW_IPR_IC_PERR_STAT, // inst cache parity error status register 76 RAW_IPR_PMCTR, // performance counter register |
| 77 78 // PAL temporary registers... 79 // register meanings gleaned from osfpal.s source code | 77 78 // PAL temporary registers... 79 // register meanings gleaned from osfpal.s source code |
| 80 RAW_IPR_PALtemp0, // local scratch 81 RAW_IPR_PALtemp1, // local scratch 82 RAW_IPR_PALtemp2, // entUna 83 RAW_IPR_PALtemp3, // CPU specific impure area pointer 84 RAW_IPR_PALtemp4, // memory management temp 85 RAW_IPR_PALtemp5, // memory management temp 86 RAW_IPR_PALtemp6, // memory management temp 87 RAW_IPR_PALtemp7, // entIF 88 RAW_IPR_PALtemp8, // intmask 89 RAW_IPR_PALtemp9, // entSys 90 RAW_IPR_PALtemp10, // ?? 91 RAW_IPR_PALtemp11, // entInt 92 RAW_IPR_PALtemp12, // entArith 93 RAW_IPR_PALtemp13, // reserved for platform specific PAL 94 RAW_IPR_PALtemp14, // reserved for platform specific PAL 95 RAW_IPR_PALtemp15, // reserved for platform specific PAL 96 RAW_IPR_PALtemp16, // scratch / whami<7:0> / mces<4:0> 97 RAW_IPR_PALtemp17, // sysval 98 RAW_IPR_PALtemp18, // usp 99 RAW_IPR_PALtemp19, // ksp 100 RAW_IPR_PALtemp20, // PTBR 101 RAW_IPR_PALtemp21, // entMM 102 RAW_IPR_PALtemp22, // kgp 103 RAW_IPR_PALtemp23, // PCBB | 80 RAW_IPR_PALtemp0, // local scratch 81 RAW_IPR_PALtemp1, // local scratch 82 RAW_IPR_PALtemp2, // entUna 83 RAW_IPR_PALtemp3, // CPU specific impure area pointer 84 RAW_IPR_PALtemp4, // memory management temp 85 RAW_IPR_PALtemp5, // memory management temp 86 RAW_IPR_PALtemp6, // memory management temp 87 RAW_IPR_PALtemp7, // entIF 88 RAW_IPR_PALtemp8, // intmask 89 RAW_IPR_PALtemp9, // entSys 90 RAW_IPR_PALtemp10, // ?? 91 RAW_IPR_PALtemp11, // entInt 92 RAW_IPR_PALtemp12, // entArith 93 RAW_IPR_PALtemp13, // reserved for platform specific PAL 94 RAW_IPR_PALtemp14, // reserved for platform specific PAL 95 RAW_IPR_PALtemp15, // reserved for platform specific PAL 96 RAW_IPR_PALtemp16, // scratch / whami<7:0> / mces<4:0> 97 RAW_IPR_PALtemp17, // sysval 98 RAW_IPR_PALtemp18, // usp 99 RAW_IPR_PALtemp19, // ksp 100 RAW_IPR_PALtemp20, // PTBR 101 RAW_IPR_PALtemp21, // entMM 102 RAW_IPR_PALtemp22, // kgp 103 RAW_IPR_PALtemp23, // PCBB |
| 104 | 104 |
| 105 RAW_IPR_DTB_ASN, // DTLB address space number register 106 RAW_IPR_DTB_CM, // DTLB current mode register 107 RAW_IPR_DTB_TAG, // DTLB tag register 108 RAW_IPR_DTB_PTE, // DTLB page table entry register | 105 RAW_IPR_DTB_ASN, // DTLB address space number register 106 RAW_IPR_DTB_CM, // DTLB current mode register 107 RAW_IPR_DTB_TAG, // DTLB tag register 108 RAW_IPR_DTB_PTE, // DTLB page table entry register |
| 109 | 109 |
| 110 RAW_IPR_VA, // fault virtual address register 111 RAW_IPR_VA_FORM, // formatted virtual address register 112 RAW_IPR_MVPTBR, // MTU virtual page table base register 113 RAW_IPR_DTB_IS, // DTLB invalidate single register 114 RAW_IPR_CC, // cycle counter register 115 RAW_IPR_CC_CTL, // cycle counter control register 116 RAW_IPR_MCSR, // MTU control register | 110 RAW_IPR_VA, // fault virtual address register 111 RAW_IPR_VA_FORM, // formatted virtual address register 112 RAW_IPR_MVPTBR, // MTU virtual page table base register 113 RAW_IPR_DTB_IS, // DTLB invalidate single register 114 RAW_IPR_CC, // cycle counter register 115 RAW_IPR_CC_CTL, // cycle counter control register 116 RAW_IPR_MCSR, // MTU control register |
| 117 | 117 |
| 118 RAW_IPR_DC_PERR_STAT, // Dcache parity error status register 119 RAW_IPR_DC_TEST_CTL, // Dcache test tag control register 120 RAW_IPR_DC_TEST_TAG, // Dcache test tag register | 118 RAW_IPR_DC_PERR_STAT, // Dcache parity error status register 119 RAW_IPR_DC_TEST_CTL, // Dcache test tag control register 120 RAW_IPR_DC_TEST_TAG, // Dcache test tag register |
| 121 RAW_IPR_DC_TEST_TAG_TEMP, // Dcache test tag temporary register | 121 RAW_IPR_DC_TEST_TAG_TEMP, // Dcache test tag temporary register |
| 122 RAW_IPR_DC_MODE, // Dcache mode register 123 RAW_IPR_MAF_MODE // miss address file mode register | 122 RAW_IPR_DC_MODE, // Dcache mode register 123 RAW_IPR_MAF_MODE // miss address file mode register |
| 124 }; 125 126 int IprToMiscRegIndex[MaxInternalProcRegs]; 127 128 void initializeIprTable() 129 { 130 static bool initialized = false; 131 if(initialized) 132 return; 133 134 memset(IprToMiscRegIndex, -1, MaxInternalProcRegs * sizeof(int)); 135 136 for(int x = 0; x < NumInternalProcRegs; x++) 137 IprToMiscRegIndex[MiscRegIndexToIpr[x]] = x; 138 } 139} 140 | 124 }; 125 126 int IprToMiscRegIndex[MaxInternalProcRegs]; 127 128 void initializeIprTable() 129 { 130 static bool initialized = false; 131 if(initialized) 132 return; 133 134 memset(IprToMiscRegIndex, -1, MaxInternalProcRegs * sizeof(int)); 135 136 for(int x = 0; x < NumInternalProcRegs; x++) 137 IprToMiscRegIndex[MiscRegIndexToIpr[x]] = x; 138 } 139} 140 |