interrupts.hh (4172:141705d83494) | interrupts.hh (5565:445da0b17433) |
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1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 23 unchanged lines hidden (view full) --- 32#ifndef __ARCH_ALPHA_INTERRUPT_HH__ 33#define __ARCH_ALPHA_INTERRUPT_HH__ 34 35#include "arch/alpha/faults.hh" 36#include "arch/alpha/isa_traits.hh" 37#include "base/compiler.hh" 38#include "cpu/thread_context.hh" 39 | 1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 23 unchanged lines hidden (view full) --- 32#ifndef __ARCH_ALPHA_INTERRUPT_HH__ 33#define __ARCH_ALPHA_INTERRUPT_HH__ 34 35#include "arch/alpha/faults.hh" 36#include "arch/alpha/isa_traits.hh" 37#include "base/compiler.hh" 38#include "cpu/thread_context.hh" 39 |
40namespace AlphaISA | 40namespace AlphaISA { 41 42class Interrupts |
41{ | 43{ |
42 class Interrupts 43 { 44 protected: 45 uint64_t interrupts[NumInterruptLevels]; 46 uint64_t intstatus; | 44 private: 45 bool newInfoSet; 46 int newIpl; 47 int newSummary; |
47 | 48 |
48 public: 49 Interrupts() 50 { 51 memset(interrupts, 0, sizeof(interrupts)); 52 intstatus = 0; 53 newInfoSet = false; 54 } | 49 protected: 50 uint64_t interrupts[NumInterruptLevels]; 51 uint64_t intstatus; |
55 | 52 |
56 void post(int int_num, int index) 57 { 58 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); | 53 public: 54 Interrupts() 55 { 56 memset(interrupts, 0, sizeof(interrupts)); 57 intstatus = 0; 58 newInfoSet = false; 59 } |
59 | 60 |
60 if (int_num < 0 || int_num >= NumInterruptLevels) 61 panic("int_num out of bounds\n"); | 61 void 62 post(int int_num, int index) 63 { 64 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); |
62 | 65 |
63 if (index < 0 || index >= sizeof(uint64_t) * 8) 64 panic("int_num out of bounds\n"); | 66 if (int_num < 0 || int_num >= NumInterruptLevels) 67 panic("int_num out of bounds\n"); |
65 | 68 |
66 interrupts[int_num] |= 1 << index; 67 intstatus |= (ULL(1) << int_num); 68 } | 69 if (index < 0 || index >= (int)sizeof(uint64_t) * 8) 70 panic("int_num out of bounds\n"); |
69 | 71 |
70 void clear(int int_num, int index) 71 { 72 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); | 72 interrupts[int_num] |= 1 << index; 73 intstatus |= (ULL(1) << int_num); 74 } |
73 | 75 |
74 if (int_num < 0 || int_num >= TheISA::NumInterruptLevels) 75 panic("int_num out of bounds\n"); | 76 void 77 clear(int int_num, int index) 78 { 79 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); |
76 | 80 |
77 if (index < 0 || index >= sizeof(uint64_t) * 8) 78 panic("int_num out of bounds\n"); | 81 if (int_num < 0 || int_num >= TheISA::NumInterruptLevels) 82 panic("int_num out of bounds\n"); |
79 | 83 |
80 interrupts[int_num] &= ~(1 << index); 81 if (interrupts[int_num] == 0) 82 intstatus &= ~(ULL(1) << int_num); 83 } | 84 if (index < 0 || index >= (int)sizeof(uint64_t) * 8) 85 panic("int_num out of bounds\n"); |
84 | 86 |
85 void clear_all() 86 { 87 DPRINTF(Interrupt, "Interrupts all cleared\n"); | 87 interrupts[int_num] &= ~(1 << index); 88 if (interrupts[int_num] == 0) 89 intstatus &= ~(ULL(1) << int_num); 90 } |
88 | 91 |
89 memset(interrupts, 0, sizeof(interrupts)); 90 intstatus = 0; 91 } | 92 void 93 clear_all() 94 { 95 DPRINTF(Interrupt, "Interrupts all cleared\n"); |
92 | 96 |
93 void serialize(std::ostream &os) 94 { 95 SERIALIZE_ARRAY(interrupts, NumInterruptLevels); 96 SERIALIZE_SCALAR(intstatus); 97 } | 97 memset(interrupts, 0, sizeof(interrupts)); 98 intstatus = 0; 99 } |
98 | 100 |
99 void unserialize(Checkpoint *cp, const std::string §ion) 100 { 101 UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels); 102 UNSERIALIZE_SCALAR(intstatus); 103 } | 101 void 102 serialize(std::ostream &os) 103 { 104 SERIALIZE_ARRAY(interrupts, NumInterruptLevels); 105 SERIALIZE_SCALAR(intstatus); 106 } |
104 | 107 |
105 bool check_interrupts(ThreadContext * tc) const 106 { 107 return (intstatus != 0) && !(tc->readPC() & 0x3); 108 } | 108 void 109 unserialize(Checkpoint *cp, const std::string §ion) 110 { 111 UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels); 112 UNSERIALIZE_SCALAR(intstatus); 113 } |
109 | 114 |
110 Fault getInterrupt(ThreadContext * tc) 111 { 112 int ipl = 0; 113 int summary = 0; | 115 bool 116 check_interrupts(ThreadContext *tc) const 117 { 118 return (intstatus != 0) && !(tc->readPC() & 0x3); 119 } |
114 | 120 |
115 if (tc->readMiscRegNoEffect(IPR_ASTRR)) 116 panic("asynchronous traps not implemented\n"); | 121 Fault 122 getInterrupt(ThreadContext *tc) 123 { 124 int ipl = 0; 125 int summary = 0; |
117 | 126 |
118 if (tc->readMiscRegNoEffect(IPR_SIRR)) { 119 for (int i = INTLEVEL_SOFTWARE_MIN; 120 i < INTLEVEL_SOFTWARE_MAX; i++) { 121 if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) { 122 // See table 4-19 of 21164 hardware reference 123 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; 124 summary |= (ULL(1) << i); 125 } | 127 if (tc->readMiscRegNoEffect(IPR_ASTRR)) 128 panic("asynchronous traps not implemented\n"); 129 130 if (tc->readMiscRegNoEffect(IPR_SIRR)) { 131 for (int i = INTLEVEL_SOFTWARE_MIN; 132 i < INTLEVEL_SOFTWARE_MAX; i++) { 133 if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) { 134 // See table 4-19 of 21164 hardware reference 135 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; 136 summary |= (ULL(1) << i); |
126 } 127 } | 137 } 138 } |
139 } |
|
128 | 140 |
129 uint64_t interrupts = intstatus; 130 if (interrupts) { 131 for (int i = INTLEVEL_EXTERNAL_MIN; 132 i < INTLEVEL_EXTERNAL_MAX; i++) { 133 if (interrupts & (ULL(1) << i)) { 134 // See table 4-19 of 21164 hardware reference 135 ipl = i; 136 summary |= (ULL(1) << i); 137 } | 141 uint64_t interrupts = intstatus; 142 if (interrupts) { 143 for (int i = INTLEVEL_EXTERNAL_MIN; 144 i < INTLEVEL_EXTERNAL_MAX; i++) { 145 if (interrupts & (ULL(1) << i)) { 146 // See table 4-19 of 21164 hardware reference 147 ipl = i; 148 summary |= (ULL(1) << i); |
138 } 139 } | 149 } 150 } |
151 } |
|
140 | 152 |
141 if (ipl && ipl > tc->readMiscRegNoEffect(IPR_IPLR)) { 142 newIpl = ipl; 143 newSummary = summary; 144 newInfoSet = true; 145 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", 146 tc->readMiscRegNoEffect(IPR_IPLR), ipl, summary); | 153 if (ipl && ipl > tc->readMiscRegNoEffect(IPR_IPLR)) { 154 newIpl = ipl; 155 newSummary = summary; 156 newInfoSet = true; 157 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", 158 tc->readMiscRegNoEffect(IPR_IPLR), ipl, summary); |
147 | 159 |
148 return new InterruptFault; 149 } else { 150 return NoFault; 151 } | 160 return new InterruptFault; 161 } else { 162 return NoFault; |
152 } | 163 } |
164 } |
|
153 | 165 |
154 void updateIntrInfo(ThreadContext *tc) 155 { 156 assert(newInfoSet); 157 tc->setMiscRegNoEffect(IPR_ISR, newSummary); 158 tc->setMiscRegNoEffect(IPR_INTID, newIpl); 159 newInfoSet = false; 160 } | 166 void 167 updateIntrInfo(ThreadContext *tc) 168 { 169 assert(newInfoSet); 170 tc->setMiscRegNoEffect(IPR_ISR, newSummary); 171 tc->setMiscRegNoEffect(IPR_INTID, newIpl); 172 newInfoSet = false; 173 } |
161 | 174 |
162 uint64_t get_vec(int int_num) 163 { 164 panic("Shouldn't be called for Alpha\n"); 165 M5_DUMMY_RETURN 166 } | 175 uint64_t 176 get_vec(int int_num) 177 { 178 panic("Shouldn't be called for Alpha\n"); 179 M5_DUMMY_RETURN; 180 } 181}; |
167 | 182 |
168 private: 169 bool newInfoSet; 170 int newIpl; 171 int newSummary; 172 }; 173} | 183} // namespace AlphaISA |
174 | 184 |
175#endif | 185#endif // __ARCH_ALPHA_INTERRUPT_HH__ |
176 | 186 |