interrupts.hh (4103:785279436bdd) interrupts.hh (4172:141705d83494)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 98 unchanged lines hidden (view full) ---

107 return (intstatus != 0) && !(tc->readPC() & 0x3);
108 }
109
110 Fault getInterrupt(ThreadContext * tc)
111 {
112 int ipl = 0;
113 int summary = 0;
114
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 98 unchanged lines hidden (view full) ---

107 return (intstatus != 0) && !(tc->readPC() & 0x3);
108 }
109
110 Fault getInterrupt(ThreadContext * tc)
111 {
112 int ipl = 0;
113 int summary = 0;
114
115 if (tc->readMiscReg(IPR_ASTRR))
115 if (tc->readMiscRegNoEffect(IPR_ASTRR))
116 panic("asynchronous traps not implemented\n");
117
116 panic("asynchronous traps not implemented\n");
117
118 if (tc->readMiscReg(IPR_SIRR)) {
118 if (tc->readMiscRegNoEffect(IPR_SIRR)) {
119 for (int i = INTLEVEL_SOFTWARE_MIN;
120 i < INTLEVEL_SOFTWARE_MAX; i++) {
119 for (int i = INTLEVEL_SOFTWARE_MIN;
120 i < INTLEVEL_SOFTWARE_MAX; i++) {
121 if (tc->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
121 if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
122 // See table 4-19 of 21164 hardware reference
123 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
124 summary |= (ULL(1) << i);
125 }
126 }
127 }
128
129 uint64_t interrupts = intstatus;
130 if (interrupts) {
131 for (int i = INTLEVEL_EXTERNAL_MIN;
132 i < INTLEVEL_EXTERNAL_MAX; i++) {
133 if (interrupts & (ULL(1) << i)) {
134 // See table 4-19 of 21164 hardware reference
135 ipl = i;
136 summary |= (ULL(1) << i);
137 }
138 }
139 }
140
122 // See table 4-19 of 21164 hardware reference
123 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
124 summary |= (ULL(1) << i);
125 }
126 }
127 }
128
129 uint64_t interrupts = intstatus;
130 if (interrupts) {
131 for (int i = INTLEVEL_EXTERNAL_MIN;
132 i < INTLEVEL_EXTERNAL_MAX; i++) {
133 if (interrupts & (ULL(1) << i)) {
134 // See table 4-19 of 21164 hardware reference
135 ipl = i;
136 summary |= (ULL(1) << i);
137 }
138 }
139 }
140
141 if (ipl && ipl > tc->readMiscReg(IPR_IPLR)) {
141 if (ipl && ipl > tc->readMiscRegNoEffect(IPR_IPLR)) {
142 newIpl = ipl;
143 newSummary = summary;
144 newInfoSet = true;
145 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
142 newIpl = ipl;
143 newSummary = summary;
144 newInfoSet = true;
145 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
146 tc->readMiscReg(IPR_IPLR), ipl, summary);
146 tc->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
147
148 return new InterruptFault;
149 } else {
150 return NoFault;
151 }
152 }
153
154 void updateIntrInfo(ThreadContext *tc)
155 {
156 assert(newInfoSet);
147
148 return new InterruptFault;
149 } else {
150 return NoFault;
151 }
152 }
153
154 void updateIntrInfo(ThreadContext *tc)
155 {
156 assert(newInfoSet);
157 tc->setMiscReg(IPR_ISR, newSummary);
158 tc->setMiscReg(IPR_INTID, newIpl);
157 tc->setMiscRegNoEffect(IPR_ISR, newSummary);
158 tc->setMiscRegNoEffect(IPR_INTID, newIpl);
159 newInfoSet = false;
160 }
161
162 uint64_t get_vec(int int_num)
163 {
164 panic("Shouldn't be called for Alpha\n");
165 M5_DUMMY_RETURN
166 }
167
168 private:
169 bool newInfoSet;
170 int newIpl;
171 int newSummary;
172 };
173}
174
175#endif
176
159 newInfoSet = false;
160 }
161
162 uint64_t get_vec(int int_num)
163 {
164 panic("Shouldn't be called for Alpha\n");
165 M5_DUMMY_RETURN
166 }
167
168 private:
169 bool newInfoSet;
170 int newIpl;
171 int newSummary;
172 };
173}
174
175#endif
176