interrupts.hh (10905:a6ca6831e775) interrupts.hh (11566:b11410957c9e)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 123 unchanged lines hidden (view full) ---

132 {
133 UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels);
134 UNSERIALIZE_SCALAR(intstatus);
135 }
136
137 bool
138 checkInterrupts(ThreadContext *tc) const
139 {
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 123 unchanged lines hidden (view full) ---

132 {
133 UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels);
134 UNSERIALIZE_SCALAR(intstatus);
135 }
136
137 bool
138 checkInterrupts(ThreadContext *tc) const
139 {
140 return (intstatus != 0) && !(tc->pcState().pc() & 0x3);
141 }
140 if (intstatus == 0)
141 return false;
142
142
143 Fault
144 getInterrupt(ThreadContext *tc)
145 {
146 uint64_t ipl = 0;
147 uint64_t summary = 0;
143 if (tc->pcState().pc() & 0x3)
144 return false;
148
149 if (tc->readMiscRegNoEffect(IPR_ASTRR))
150 panic("asynchronous traps not implemented\n");
151
145
146 if (tc->readMiscRegNoEffect(IPR_ASTRR))
147 panic("asynchronous traps not implemented\n");
148
149 uint64_t ipl = 0;
150 uint64_t summary = 0;
151
152 if (tc->readMiscRegNoEffect(IPR_SIRR)) {
153 for (uint64_t i = INTLEVEL_SOFTWARE_MIN;
154 i < INTLEVEL_SOFTWARE_MAX; i++) {
155 if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
156 // See table 4-19 of 21164 hardware reference
157 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
158 summary |= (ULL(1) << i);
159 }
160 }
161 }
162
152 if (tc->readMiscRegNoEffect(IPR_SIRR)) {
153 for (uint64_t i = INTLEVEL_SOFTWARE_MIN;
154 i < INTLEVEL_SOFTWARE_MAX; i++) {
155 if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
156 // See table 4-19 of 21164 hardware reference
157 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
158 summary |= (ULL(1) << i);
159 }
160 }
161 }
162
163 if (intstatus) {
164 for (uint64_t i = INTLEVEL_EXTERNAL_MIN;
165 i < INTLEVEL_EXTERNAL_MAX; i++) {
166 if (intstatus & (ULL(1) << i)) {
163 for (uint64_t i = INTLEVEL_EXTERNAL_MIN; i < INTLEVEL_EXTERNAL_MAX;
164 i++) {
165 if (intstatus & (ULL(1) << i)) {
166 // See table 4-19 of 21164 hardware reference
167 ipl = i;
168 summary |= (ULL(1) << i);
169 }
170 }
171
172 return ipl && ipl > tc->readMiscRegNoEffect(IPR_IPLR);
173 }
174
175 Fault
176 getInterrupt(ThreadContext *tc)
177 {
178 assert(checkInterrupts(tc));
179
180 uint64_t ipl = 0;
181 uint64_t summary = 0;
182 if (tc->readMiscRegNoEffect(IPR_SIRR)) {
183 for (uint64_t i = INTLEVEL_SOFTWARE_MIN;
184 i < INTLEVEL_SOFTWARE_MAX; i++) {
185 if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
167 // See table 4-19 of 21164 hardware reference
186 // See table 4-19 of 21164 hardware reference
168 ipl = i;
187 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
169 summary |= (ULL(1) << i);
170 }
171 }
172 }
173
188 summary |= (ULL(1) << i);
189 }
190 }
191 }
192
174 if (ipl && ipl > tc->readMiscRegNoEffect(IPR_IPLR)) {
175 newIpl = ipl;
176 newSummary = summary;
177 newInfoSet = true;
178 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
179 tc->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
180
181 return std::make_shared<InterruptFault>();
182 } else {
183 return NoFault;
193 for (uint64_t i = INTLEVEL_EXTERNAL_MIN; i < INTLEVEL_EXTERNAL_MAX;
194 i++) {
195 if (intstatus & (ULL(1) << i)) {
196 // See table 4-19 of 21164 hardware reference
197 ipl = i;
198 summary |= (ULL(1) << i);
199 }
184 }
200 }
201
202 newIpl = ipl;
203 newSummary = summary;
204 newInfoSet = true;
205 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
206 tc->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
207
208 return std::make_shared<InterruptFault>();
185 }
186
187 void
188 updateIntrInfo(ThreadContext *tc)
189 {
190 assert(newInfoSet);
191 tc->setMiscRegNoEffect(IPR_ISR, newSummary);
192 tc->setMiscRegNoEffect(IPR_INTID, newIpl);
193 newInfoSet = false;
194 }
195};
196
197} // namespace AlphaISA
198
199#endif // __ARCH_ALPHA_INTERRUPT_HH__
200
209 }
210
211 void
212 updateIntrInfo(ThreadContext *tc)
213 {
214 assert(newInfoSet);
215 tc->setMiscRegNoEffect(IPR_ISR, newSummary);
216 tc->setMiscRegNoEffect(IPR_INTID, newIpl);
217 newInfoSet = false;
218 }
219};
220
221} // namespace AlphaISA
222
223#endif // __ARCH_ALPHA_INTERRUPT_HH__
224