1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 125 unchanged lines hidden (view full) --- 134 checkInterrupts(ThreadContext *tc) const 135 { 136 return (intstatus != 0) && !(tc->readPC() & 0x3); 137 } 138 139 Fault 140 getInterrupt(ThreadContext *tc) 141 { |
142 uint64_t ipl = 0; 143 uint64_t summary = 0; |
144 145 if (tc->readMiscRegNoEffect(IPR_ASTRR)) 146 panic("asynchronous traps not implemented\n"); 147 148 if (tc->readMiscRegNoEffect(IPR_SIRR)) { |
149 for (uint64_t i = INTLEVEL_SOFTWARE_MIN; |
150 i < INTLEVEL_SOFTWARE_MAX; i++) { 151 if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) { 152 // See table 4-19 of 21164 hardware reference 153 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; 154 summary |= (ULL(1) << i); 155 } 156 } 157 } 158 159 uint64_t interrupts = intstatus; 160 if (interrupts) { |
161 for (uint64_t i = INTLEVEL_EXTERNAL_MIN; |
162 i < INTLEVEL_EXTERNAL_MAX; i++) { 163 if (interrupts & (ULL(1) << i)) { 164 // See table 4-19 of 21164 hardware reference 165 ipl = i; 166 summary |= (ULL(1) << i); 167 } 168 } 169 } --- 28 unchanged lines hidden --- |