1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Kevin Lim
30 */
31
32#ifndef __ARCH_ALPHA_INTERRUPT_HH__
33#define __ARCH_ALPHA_INTERRUPT_HH__
34
35#include "arch/alpha/faults.hh"
36#include "arch/alpha/isa_traits.hh"
37#include "base/compiler.hh"
38#include "base/trace.hh"
39#include "cpu/thread_context.hh"
40#include "params/AlphaInterrupts.hh"
41#include "sim/sim_object.hh"
42
43namespace AlphaISA {
44
45class Interrupts : public SimObject
46{
47 private:
48 bool newInfoSet;
49 int newIpl;
50 int newSummary;
51 BaseCPU * cpu;
52
53 protected:
54 uint64_t interrupts[NumInterruptLevels];
55 uint64_t intstatus;
56
57 public:
58 typedef AlphaInterruptsParams Params;
59
60 const Params *
61 params() const
62 {
63 return dynamic_cast<const Params *>(_params);
64 }
65
66 Interrupts(Params * p) : SimObject(p), cpu(NULL)
67 {
68 memset(interrupts, 0, sizeof(interrupts));
69 intstatus = 0;
70 newInfoSet = false;
71 }
72
73 void
74 setCPU(BaseCPU * _cpu)
75 {
76 cpu = _cpu;
77 }
78
79 void
80 post(int int_num, int index)
81 {
82 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
83
84 if (int_num < 0 || int_num >= NumInterruptLevels)
85 panic("int_num out of bounds\n");
86
87 if (index < 0 || index >= (int)sizeof(uint64_t) * 8)
88 panic("int_num out of bounds\n");
89
90 interrupts[int_num] |= 1 << index;
91 intstatus |= (ULL(1) << int_num);
92 }
93
94 void
95 clear(int int_num, int index)
96 {
97 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
98
99 if (int_num < 0 || int_num >= NumInterruptLevels)
100 panic("int_num out of bounds\n");
101
102 if (index < 0 || index >= (int)sizeof(uint64_t) * 8)
103 panic("int_num out of bounds\n");
104
105 interrupts[int_num] &= ~(1 << index);
106 if (interrupts[int_num] == 0)
107 intstatus &= ~(ULL(1) << int_num);
108 }
109
110 void
111 clearAll()
112 {
113 DPRINTF(Interrupt, "Interrupts all cleared\n");
114
115 memset(interrupts, 0, sizeof(interrupts));
116 intstatus = 0;
117 }
118
119 void
120 serialize(std::ostream &os)
121 {
122 SERIALIZE_ARRAY(interrupts, NumInterruptLevels);
123 SERIALIZE_SCALAR(intstatus);
124 }
125
126 void
127 unserialize(Checkpoint *cp, const std::string §ion)
128 {
129 UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels);
130 UNSERIALIZE_SCALAR(intstatus);
131 }
132
133 bool
134 checkInterrupts(ThreadContext *tc) const
135 {
136 return (intstatus != 0) && !(tc->readPC() & 0x3);
137 }
138
139 Fault
140 getInterrupt(ThreadContext *tc)
141 {
| 1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Kevin Lim
30 */
31
32#ifndef __ARCH_ALPHA_INTERRUPT_HH__
33#define __ARCH_ALPHA_INTERRUPT_HH__
34
35#include "arch/alpha/faults.hh"
36#include "arch/alpha/isa_traits.hh"
37#include "base/compiler.hh"
38#include "base/trace.hh"
39#include "cpu/thread_context.hh"
40#include "params/AlphaInterrupts.hh"
41#include "sim/sim_object.hh"
42
43namespace AlphaISA {
44
45class Interrupts : public SimObject
46{
47 private:
48 bool newInfoSet;
49 int newIpl;
50 int newSummary;
51 BaseCPU * cpu;
52
53 protected:
54 uint64_t interrupts[NumInterruptLevels];
55 uint64_t intstatus;
56
57 public:
58 typedef AlphaInterruptsParams Params;
59
60 const Params *
61 params() const
62 {
63 return dynamic_cast<const Params *>(_params);
64 }
65
66 Interrupts(Params * p) : SimObject(p), cpu(NULL)
67 {
68 memset(interrupts, 0, sizeof(interrupts));
69 intstatus = 0;
70 newInfoSet = false;
71 }
72
73 void
74 setCPU(BaseCPU * _cpu)
75 {
76 cpu = _cpu;
77 }
78
79 void
80 post(int int_num, int index)
81 {
82 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
83
84 if (int_num < 0 || int_num >= NumInterruptLevels)
85 panic("int_num out of bounds\n");
86
87 if (index < 0 || index >= (int)sizeof(uint64_t) * 8)
88 panic("int_num out of bounds\n");
89
90 interrupts[int_num] |= 1 << index;
91 intstatus |= (ULL(1) << int_num);
92 }
93
94 void
95 clear(int int_num, int index)
96 {
97 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
98
99 if (int_num < 0 || int_num >= NumInterruptLevels)
100 panic("int_num out of bounds\n");
101
102 if (index < 0 || index >= (int)sizeof(uint64_t) * 8)
103 panic("int_num out of bounds\n");
104
105 interrupts[int_num] &= ~(1 << index);
106 if (interrupts[int_num] == 0)
107 intstatus &= ~(ULL(1) << int_num);
108 }
109
110 void
111 clearAll()
112 {
113 DPRINTF(Interrupt, "Interrupts all cleared\n");
114
115 memset(interrupts, 0, sizeof(interrupts));
116 intstatus = 0;
117 }
118
119 void
120 serialize(std::ostream &os)
121 {
122 SERIALIZE_ARRAY(interrupts, NumInterruptLevels);
123 SERIALIZE_SCALAR(intstatus);
124 }
125
126 void
127 unserialize(Checkpoint *cp, const std::string §ion)
128 {
129 UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels);
130 UNSERIALIZE_SCALAR(intstatus);
131 }
132
133 bool
134 checkInterrupts(ThreadContext *tc) const
135 {
136 return (intstatus != 0) && !(tc->readPC() & 0x3);
137 }
138
139 Fault
140 getInterrupt(ThreadContext *tc)
141 {
|
162 i < INTLEVEL_EXTERNAL_MAX; i++) {
163 if (interrupts & (ULL(1) << i)) {
164 // See table 4-19 of 21164 hardware reference
165 ipl = i;
166 summary |= (ULL(1) << i);
167 }
168 }
169 }
170
171 if (ipl && ipl > tc->readMiscRegNoEffect(IPR_IPLR)) {
172 newIpl = ipl;
173 newSummary = summary;
174 newInfoSet = true;
175 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
176 tc->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
177
178 return new InterruptFault;
179 } else {
180 return NoFault;
181 }
182 }
183
184 void
185 updateIntrInfo(ThreadContext *tc)
186 {
187 assert(newInfoSet);
188 tc->setMiscRegNoEffect(IPR_ISR, newSummary);
189 tc->setMiscRegNoEffect(IPR_INTID, newIpl);
190 newInfoSet = false;
191 }
192};
193
194} // namespace AlphaISA
195
196#endif // __ARCH_ALPHA_INTERRUPT_HH__
197
| 162 i < INTLEVEL_EXTERNAL_MAX; i++) {
163 if (interrupts & (ULL(1) << i)) {
164 // See table 4-19 of 21164 hardware reference
165 ipl = i;
166 summary |= (ULL(1) << i);
167 }
168 }
169 }
170
171 if (ipl && ipl > tc->readMiscRegNoEffect(IPR_IPLR)) {
172 newIpl = ipl;
173 newSummary = summary;
174 newInfoSet = true;
175 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
176 tc->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
177
178 return new InterruptFault;
179 } else {
180 return NoFault;
181 }
182 }
183
184 void
185 updateIntrInfo(ThreadContext *tc)
186 {
187 assert(newInfoSet);
188 tc->setMiscRegNoEffect(IPR_ISR, newSummary);
189 tc->setMiscRegNoEffect(IPR_INTID, newIpl);
190 newInfoSet = false;
191 }
192};
193
194} // namespace AlphaISA
195
196#endif // __ARCH_ALPHA_INTERRUPT_HH__
197
|