1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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44 uint64_t interrupts[NumInterruptLevels];
45 uint64_t intstatus;
46
47 public:
48 Interrupts()
49 {
50 memset(interrupts, 0, sizeof(interrupts));
51 intstatus = 0;
52 }
53
54 void post(int int_num, int index)
55 {
56 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
57
58 if (int_num < 0 || int_num >= NumInterruptLevels)
59 panic("int_num out of bounds\n");

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132 // See table 4-19 of 21164 hardware reference
133 ipl = i;
134 summary |= (ULL(1) << i);
135 }
136 }
137 }
138
139 if (ipl && ipl > tc->readMiscReg(IPR_IPLR)) {
140 tc->setMiscReg(IPR_ISR, summary);
141 tc->setMiscReg(IPR_INTID, ipl);
142
143 /* The following needs to be added back in somehow */
144 // Checker needs to know these two registers were updated.
145/*#if USE_CHECKER
146 if (this->checker) {
147 this->checker->threadBase()->setMiscReg(IPR_ISR, summary);
148 this->checker->threadBase()->setMiscReg(IPR_INTID, ipl);
149 }
150#endif*/
151
152 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
153 tc->readMiscReg(IPR_IPLR), ipl, summary);
154
155 return new InterruptFault;
156 } else {
157 return NoFault;
158 }
159 }
160
161 private:
162 };
163}
164
165#endif
166