faults.cc (8806:669e93d79ed9) faults.cc (10417:710ee116eb68)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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101FaultVect PalFault::_vect = 0x2001;
102FaultStat PalFault::_count;
103
104FaultName IntegerOverflowFault::_name = "intover";
105FaultVect IntegerOverflowFault::_vect = 0x0501;
106FaultStat IntegerOverflowFault::_count;
107
108void
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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101FaultVect PalFault::_vect = 0x2001;
102FaultStat PalFault::_count;
103
104FaultName IntegerOverflowFault::_name = "intover";
105FaultVect IntegerOverflowFault::_vect = 0x0501;
106FaultStat IntegerOverflowFault::_count;
107
108void
109AlphaFault::invoke(ThreadContext *tc, StaticInstPtr inst)
109AlphaFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
110{
111 FaultBase::invoke(tc);
112 if (!FullSystem)
113 return;
114 countStat()++;
115
116 PCState pc = tc->pcState();
117

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125 tc->readMiscRegNoEffect(IPR_EXC_ADDR) + 4);
126 }
127
128 pc.set(tc->readMiscRegNoEffect(IPR_PAL_BASE) + vect());
129 tc->pcState(pc);
130}
131
132void
110{
111 FaultBase::invoke(tc);
112 if (!FullSystem)
113 return;
114 countStat()++;
115
116 PCState pc = tc->pcState();
117

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125 tc->readMiscRegNoEffect(IPR_EXC_ADDR) + 4);
126 }
127
128 pc.set(tc->readMiscRegNoEffect(IPR_PAL_BASE) + vect());
129 tc->pcState(pc);
130}
131
132void
133ArithmeticFault::invoke(ThreadContext *tc, StaticInstPtr inst)
133ArithmeticFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
134{
135 FaultBase::invoke(tc);
136 if (!FullSystem)
137 return;
138 panic("Arithmetic traps are unimplemented!");
139}
140
141void
134{
135 FaultBase::invoke(tc);
136 if (!FullSystem)
137 return;
138 panic("Arithmetic traps are unimplemented!");
139}
140
141void
142DtbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
142DtbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
143{
144 if (FullSystem) {
145 // Set fault address and flags. Even though we're modeling an
146 // EV5, we use the EV6 technique of not latching fault registers
147 // on VPTE loads (instead of locking the registers until IPR_VA is
148 // read, like the EV5). The EV6 approach is cleaner and seems to
149 // work with EV5 PAL code, but not the other way around.
150 if (!tc->misspeculating() &&

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164 tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
165 }
166 }
167
168 AlphaFault::invoke(tc);
169}
170
171void
143{
144 if (FullSystem) {
145 // Set fault address and flags. Even though we're modeling an
146 // EV5, we use the EV6 technique of not latching fault registers
147 // on VPTE loads (instead of locking the registers until IPR_VA is
148 // read, like the EV5). The EV6 approach is cleaner and seems to
149 // work with EV5 PAL code, but not the other way around.
150 if (!tc->misspeculating() &&

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164 tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
165 }
166 }
167
168 AlphaFault::invoke(tc);
169}
170
171void
172ItbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
172ItbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
173{
174 if (FullSystem) {
175 if (!tc->misspeculating()) {
176 tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
177 tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
178 tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
179 }
180 }
181
182 AlphaFault::invoke(tc);
183}
184
185void
173{
174 if (FullSystem) {
175 if (!tc->misspeculating()) {
176 tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
177 tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
178 tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
179 }
180 }
181
182 AlphaFault::invoke(tc);
183}
184
185void
186ItbPageFault::invoke(ThreadContext *tc, StaticInstPtr inst)
186ItbPageFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
187{
188 if (FullSystem) {
189 ItbFault::invoke(tc);
190 return;
191 }
192
193 Process *p = tc->getProcessPtr();
194 TlbEntry entry;
195 bool success = p->pTable->lookup(pc, entry);
196 if (!success) {
197 panic("Tried to execute unmapped address %#x.\n", pc);
198 } else {
199 VAddr vaddr(pc);
200 tc->getITBPtr()->insert(vaddr.page(), entry);
201 }
202}
203
204void
187{
188 if (FullSystem) {
189 ItbFault::invoke(tc);
190 return;
191 }
192
193 Process *p = tc->getProcessPtr();
194 TlbEntry entry;
195 bool success = p->pTable->lookup(pc, entry);
196 if (!success) {
197 panic("Tried to execute unmapped address %#x.\n", pc);
198 } else {
199 VAddr vaddr(pc);
200 tc->getITBPtr()->insert(vaddr.page(), entry);
201 }
202}
203
204void
205NDtbMissFault::invoke(ThreadContext *tc, StaticInstPtr inst)
205NDtbMissFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
206{
207 if (FullSystem) {
208 DtbFault::invoke(tc, inst);
209 return;
210 }
211
212 Process *p = tc->getProcessPtr();
213 TlbEntry entry;

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207 if (FullSystem) {
208 DtbFault::invoke(tc, inst);
209 return;
210 }
211
212 Process *p = tc->getProcessPtr();
213 TlbEntry entry;

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