faults.cc (7676:92274350b953) faults.cc (7678:f19b6a3a8cec)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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105
106FaultName IntegerOverflowFault::_name = "intover";
107FaultVect IntegerOverflowFault::_vect = 0x0501;
108FaultStat IntegerOverflowFault::_count;
109
110#if FULL_SYSTEM
111
112void
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 96 unchanged lines hidden (view full) ---

105
106FaultName IntegerOverflowFault::_name = "intover";
107FaultVect IntegerOverflowFault::_vect = 0x0501;
108FaultStat IntegerOverflowFault::_count;
109
110#if FULL_SYSTEM
111
112void
113AlphaFault::invoke(ThreadContext *tc)
113AlphaFault::invoke(ThreadContext *tc, StaticInstPtr inst)
114{
115 FaultBase::invoke(tc);
116 countStat()++;
117
118 // exception restart address
119 if (setRestartAddress() || !(tc->readPC() & 0x3))
120 tc->setMiscRegNoEffect(IPR_EXC_ADDR, tc->readPC());
121
122 if (skipFaultingInstruction()) {
123 // traps... skip faulting instruction.
124 tc->setMiscRegNoEffect(IPR_EXC_ADDR,
125 tc->readMiscRegNoEffect(IPR_EXC_ADDR) + 4);
126 }
127
128 tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + vect());
129 tc->setNextPC(tc->readPC() + sizeof(MachInst));
130}
131
132void
114{
115 FaultBase::invoke(tc);
116 countStat()++;
117
118 // exception restart address
119 if (setRestartAddress() || !(tc->readPC() & 0x3))
120 tc->setMiscRegNoEffect(IPR_EXC_ADDR, tc->readPC());
121
122 if (skipFaultingInstruction()) {
123 // traps... skip faulting instruction.
124 tc->setMiscRegNoEffect(IPR_EXC_ADDR,
125 tc->readMiscRegNoEffect(IPR_EXC_ADDR) + 4);
126 }
127
128 tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + vect());
129 tc->setNextPC(tc->readPC() + sizeof(MachInst));
130}
131
132void
133ArithmeticFault::invoke(ThreadContext *tc)
133ArithmeticFault::invoke(ThreadContext *tc, StaticInstPtr inst)
134{
135 FaultBase::invoke(tc);
136 panic("Arithmetic traps are unimplemented!");
137}
138
139void
134{
135 FaultBase::invoke(tc);
136 panic("Arithmetic traps are unimplemented!");
137}
138
139void
140DtbFault::invoke(ThreadContext *tc)
140DtbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
141{
142 // Set fault address and flags. Even though we're modeling an
143 // EV5, we use the EV6 technique of not latching fault registers
144 // on VPTE loads (instead of locking the registers until IPR_VA is
145 // read, like the EV5). The EV6 approach is cleaner and seems to
146 // work with EV5 PAL code, but not the other way around.
147 if (!tc->misspeculating() &&
148 reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
149 // set VA register with faulting address
150 tc->setMiscRegNoEffect(IPR_VA, vaddr);
151
152 // set MM_STAT register flags
141{
142 // Set fault address and flags. Even though we're modeling an
143 // EV5, we use the EV6 technique of not latching fault registers
144 // on VPTE loads (instead of locking the registers until IPR_VA is
145 // read, like the EV5). The EV6 approach is cleaner and seems to
146 // work with EV5 PAL code, but not the other way around.
147 if (!tc->misspeculating() &&
148 reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
149 // set VA register with faulting address
150 tc->setMiscRegNoEffect(IPR_VA, vaddr);
151
152 // set MM_STAT register flags
153 MachInst machInst = inst->machInst;
153 tc->setMiscRegNoEffect(IPR_MM_STAT,
154 tc->setMiscRegNoEffect(IPR_MM_STAT,
154 (((Opcode(tc->getInst()) & 0x3f) << 11) |
155 ((Ra(tc->getInst()) & 0x1f) << 6) |
155 (((Opcode(machInst) & 0x3f) << 11) |
156 ((Ra(machInst) & 0x1f) << 6) |
156 (flags & 0x3f)));
157
158 // set VA_FORM register with faulting formatted address
159 tc->setMiscRegNoEffect(IPR_VA_FORM,
160 tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
161 }
162
163 AlphaFault::invoke(tc);
164}
165
166void
157 (flags & 0x3f)));
158
159 // set VA_FORM register with faulting formatted address
160 tc->setMiscRegNoEffect(IPR_VA_FORM,
161 tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
162 }
163
164 AlphaFault::invoke(tc);
165}
166
167void
167ItbFault::invoke(ThreadContext *tc)
168ItbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
168{
169 if (!tc->misspeculating()) {
170 tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
171 tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
172 tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
173 }
174
175 AlphaFault::invoke(tc);
176}
177
178#else
179
180void
169{
170 if (!tc->misspeculating()) {
171 tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
172 tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
173 tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
174 }
175
176 AlphaFault::invoke(tc);
177}
178
179#else
180
181void
181ItbPageFault::invoke(ThreadContext *tc)
182ItbPageFault::invoke(ThreadContext *tc, StaticInstPtr inst)
182{
183 Process *p = tc->getProcessPtr();
184 TlbEntry entry;
185 bool success = p->pTable->lookup(pc, entry);
186 if (!success) {
187 panic("Tried to execute unmapped address %#x.\n", pc);
188 } else {
189 VAddr vaddr(pc);
190 tc->getITBPtr()->insert(vaddr.page(), entry);
191 }
192}
193
194void
183{
184 Process *p = tc->getProcessPtr();
185 TlbEntry entry;
186 bool success = p->pTable->lookup(pc, entry);
187 if (!success) {
188 panic("Tried to execute unmapped address %#x.\n", pc);
189 } else {
190 VAddr vaddr(pc);
191 tc->getITBPtr()->insert(vaddr.page(), entry);
192 }
193}
194
195void
195NDtbMissFault::invoke(ThreadContext *tc)
196NDtbMissFault::invoke(ThreadContext *tc, StaticInstPtr inst)
196{
197 Process *p = tc->getProcessPtr();
198 TlbEntry entry;
199 bool success = p->pTable->lookup(vaddr, entry);
200 if (!success) {
201 p->checkAndAllocNextPage(vaddr);
202 success = p->pTable->lookup(vaddr, entry);
203 }
204 if (!success) {
205 panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
206 } else {
207 tc->getDTBPtr()->insert(vaddr.page(), entry);
208 }
209}
210
211#endif
212
213} // namespace AlphaISA
214
197{
198 Process *p = tc->getProcessPtr();
199 TlbEntry entry;
200 bool success = p->pTable->lookup(vaddr, entry);
201 if (!success) {
202 p->checkAndAllocNextPage(vaddr);
203 success = p->pTable->lookup(vaddr, entry);
204 }
205 if (!success) {
206 panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
207 } else {
208 tc->getDTBPtr()->insert(vaddr.page(), entry);
209 }
210}
211
212#endif
213
214} // namespace AlphaISA
215