faults.cc (5568:d14250d688d2) faults.cc (5569:baeee670d4ce)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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35#include "cpu/thread_context.hh"
36#include "cpu/base.hh"
37#include "base/trace.hh"
38#if !FULL_SYSTEM
39#include "sim/process.hh"
40#include "mem/page_table.hh"
41#endif
42
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 26 unchanged lines hidden (view full) ---

35#include "cpu/thread_context.hh"
36#include "cpu/base.hh"
37#include "base/trace.hh"
38#if !FULL_SYSTEM
39#include "sim/process.hh"
40#include "mem/page_table.hh"
41#endif
42
43namespace AlphaISA
44{
43namespace AlphaISA {
45
46FaultName MachineCheckFault::_name = "mchk";
47FaultVect MachineCheckFault::_vect = 0x0401;
48FaultStat MachineCheckFault::_count;
49
50FaultName AlignmentFault::_name = "unalign";
51FaultVect AlignmentFault::_vect = 0x0301;
52FaultStat AlignmentFault::_count;

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104FaultStat PalFault::_count;
105
106FaultName IntegerOverflowFault::_name = "intover";
107FaultVect IntegerOverflowFault::_vect = 0x0501;
108FaultStat IntegerOverflowFault::_count;
109
110#if FULL_SYSTEM
111
44
45FaultName MachineCheckFault::_name = "mchk";
46FaultVect MachineCheckFault::_vect = 0x0401;
47FaultStat MachineCheckFault::_count;
48
49FaultName AlignmentFault::_name = "unalign";
50FaultVect AlignmentFault::_vect = 0x0301;
51FaultStat AlignmentFault::_count;

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103FaultStat PalFault::_count;
104
105FaultName IntegerOverflowFault::_name = "intover";
106FaultVect IntegerOverflowFault::_vect = 0x0501;
107FaultStat IntegerOverflowFault::_count;
108
109#if FULL_SYSTEM
110
112void AlphaFault::invoke(ThreadContext * tc)
111void
112AlphaFault::invoke(ThreadContext *tc)
113{
114 FaultBase::invoke(tc);
115 countStat()++;
116
117 // exception restart address
118 if (setRestartAddress() || !(tc->readPC() & 0x3))
119 tc->setMiscRegNoEffect(IPR_EXC_ADDR, tc->readPC());
120
121 if (skipFaultingInstruction()) {
122 // traps... skip faulting instruction.
123 tc->setMiscRegNoEffect(IPR_EXC_ADDR,
124 tc->readMiscRegNoEffect(IPR_EXC_ADDR) + 4);
125 }
126
127 tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + vect());
128 tc->setNextPC(tc->readPC() + sizeof(MachInst));
129}
130
113{
114 FaultBase::invoke(tc);
115 countStat()++;
116
117 // exception restart address
118 if (setRestartAddress() || !(tc->readPC() & 0x3))
119 tc->setMiscRegNoEffect(IPR_EXC_ADDR, tc->readPC());
120
121 if (skipFaultingInstruction()) {
122 // traps... skip faulting instruction.
123 tc->setMiscRegNoEffect(IPR_EXC_ADDR,
124 tc->readMiscRegNoEffect(IPR_EXC_ADDR) + 4);
125 }
126
127 tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + vect());
128 tc->setNextPC(tc->readPC() + sizeof(MachInst));
129}
130
131void ArithmeticFault::invoke(ThreadContext * tc)
131void
132ArithmeticFault::invoke(ThreadContext *tc)
132{
133 FaultBase::invoke(tc);
134 panic("Arithmetic traps are unimplemented!");
135}
136
133{
134 FaultBase::invoke(tc);
135 panic("Arithmetic traps are unimplemented!");
136}
137
137void DtbFault::invoke(ThreadContext * tc)
138void
139DtbFault::invoke(ThreadContext *tc)
138{
139 // Set fault address and flags. Even though we're modeling an
140 // EV5, we use the EV6 technique of not latching fault registers
141 // on VPTE loads (instead of locking the registers until IPR_VA is
142 // read, like the EV5). The EV6 approach is cleaner and seems to
143 // work with EV5 PAL code, but not the other way around.
140{
141 // Set fault address and flags. Even though we're modeling an
142 // EV5, we use the EV6 technique of not latching fault registers
143 // on VPTE loads (instead of locking the registers until IPR_VA is
144 // read, like the EV5). The EV6 approach is cleaner and seems to
145 // work with EV5 PAL code, but not the other way around.
144 if (!tc->misspeculating()
145 && !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) {
146 if (!tc->misspeculating() &&
147 !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) {
146 // set VA register with faulting address
147 tc->setMiscRegNoEffect(IPR_VA, vaddr);
148
149 // set MM_STAT register flags
150 tc->setMiscRegNoEffect(IPR_MM_STAT,
148 // set VA register with faulting address
149 tc->setMiscRegNoEffect(IPR_VA, vaddr);
150
151 // set MM_STAT register flags
152 tc->setMiscRegNoEffect(IPR_MM_STAT,
151 (((Opcode(tc->getInst()) & 0x3f) << 11)
152 | ((Ra(tc->getInst()) & 0x1f) << 6)
153 | (flags & 0x3f)));
153 (((Opcode(tc->getInst()) & 0x3f) << 11) |
154 ((Ra(tc->getInst()) & 0x1f) << 6) |
155 (flags & 0x3f)));
154
155 // set VA_FORM register with faulting formatted address
156 tc->setMiscRegNoEffect(IPR_VA_FORM,
157 tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
158 }
159
160 AlphaFault::invoke(tc);
161}
162
156
157 // set VA_FORM register with faulting formatted address
158 tc->setMiscRegNoEffect(IPR_VA_FORM,
159 tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
160 }
161
162 AlphaFault::invoke(tc);
163}
164
163void ItbFault::invoke(ThreadContext * tc)
165void
166ItbFault::invoke(ThreadContext *tc)
164{
165 if (!tc->misspeculating()) {
166 tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
167 tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
167{
168 if (!tc->misspeculating()) {
169 tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
170 tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
168 tc->readMiscRegNoEffect(IPR_IVPTBR) |
169 (VAddr(pc).vpn() << 3));
171 tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
170 }
171
172 AlphaFault::invoke(tc);
173}
174
175#else
176
172 }
173
174 AlphaFault::invoke(tc);
175}
176
177#else
178
177void ItbPageFault::invoke(ThreadContext * tc)
179void
180ItbPageFault::invoke(ThreadContext *tc)
178{
179 Process *p = tc->getProcessPtr();
180 TlbEntry entry;
181 bool success = p->pTable->lookup(pc, entry);
181{
182 Process *p = tc->getProcessPtr();
183 TlbEntry entry;
184 bool success = p->pTable->lookup(pc, entry);
182 if(!success) {
185 if (!success) {
183 panic("Tried to execute unmapped address %#x.\n", pc);
184 } else {
185 VAddr vaddr(pc);
186 tc->getITBPtr()->insert(vaddr.page(), entry);
187 }
188}
189
186 panic("Tried to execute unmapped address %#x.\n", pc);
187 } else {
188 VAddr vaddr(pc);
189 tc->getITBPtr()->insert(vaddr.page(), entry);
190 }
191}
192
190void NDtbMissFault::invoke(ThreadContext * tc)
193void
194NDtbMissFault::invoke(ThreadContext *tc)
191{
192 Process *p = tc->getProcessPtr();
193 TlbEntry entry;
194 bool success = p->pTable->lookup(vaddr, entry);
195{
196 Process *p = tc->getProcessPtr();
197 TlbEntry entry;
198 bool success = p->pTable->lookup(vaddr, entry);
195 if(!success) {
199 if (!success) {
196 p->checkAndAllocNextPage(vaddr);
197 success = p->pTable->lookup(vaddr, entry);
198 }
200 p->checkAndAllocNextPage(vaddr);
201 success = p->pTable->lookup(vaddr, entry);
202 }
199 if(!success) {
203 if (!success) {
200 panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
201 } else {
202 tc->getDTBPtr()->insert(vaddr.page(), entry);
203 }
204}
205
206#endif
207
208} // namespace AlphaISA
209
204 panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
205 } else {
206 tc->getDTBPtr()->insert(vaddr.page(), entry);
207 }
208}
209
210#endif
211
212} // namespace AlphaISA
213