faults.cc (5566:3440c9ad49b4) faults.cc (5568:d14250d688d2)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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111
112void AlphaFault::invoke(ThreadContext * tc)
113{
114 FaultBase::invoke(tc);
115 countStat()++;
116
117 // exception restart address
118 if (setRestartAddress() || !(tc->readPC() & 0x3))
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 102 unchanged lines hidden (view full) ---

111
112void AlphaFault::invoke(ThreadContext * tc)
113{
114 FaultBase::invoke(tc);
115 countStat()++;
116
117 // exception restart address
118 if (setRestartAddress() || !(tc->readPC() & 0x3))
119 tc->setMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR, tc->readPC());
119 tc->setMiscRegNoEffect(IPR_EXC_ADDR, tc->readPC());
120
121 if (skipFaultingInstruction()) {
122 // traps... skip faulting instruction.
120
121 if (skipFaultingInstruction()) {
122 // traps... skip faulting instruction.
123 tc->setMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
124 tc->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR) + 4);
123 tc->setMiscRegNoEffect(IPR_EXC_ADDR,
124 tc->readMiscRegNoEffect(IPR_EXC_ADDR) + 4);
125 }
126
125 }
126
127 tc->setPC(tc->readMiscRegNoEffect(AlphaISA::IPR_PAL_BASE) + vect());
127 tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + vect());
128 tc->setNextPC(tc->readPC() + sizeof(MachInst));
129}
130
131void ArithmeticFault::invoke(ThreadContext * tc)
132{
133 FaultBase::invoke(tc);
134 panic("Arithmetic traps are unimplemented!");
135}
136
137void DtbFault::invoke(ThreadContext * tc)
138{
139 // Set fault address and flags. Even though we're modeling an
140 // EV5, we use the EV6 technique of not latching fault registers
141 // on VPTE loads (instead of locking the registers until IPR_VA is
142 // read, like the EV5). The EV6 approach is cleaner and seems to
143 // work with EV5 PAL code, but not the other way around.
144 if (!tc->misspeculating()
145 && !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) {
146 // set VA register with faulting address
128 tc->setNextPC(tc->readPC() + sizeof(MachInst));
129}
130
131void ArithmeticFault::invoke(ThreadContext * tc)
132{
133 FaultBase::invoke(tc);
134 panic("Arithmetic traps are unimplemented!");
135}
136
137void DtbFault::invoke(ThreadContext * tc)
138{
139 // Set fault address and flags. Even though we're modeling an
140 // EV5, we use the EV6 technique of not latching fault registers
141 // on VPTE loads (instead of locking the registers until IPR_VA is
142 // read, like the EV5). The EV6 approach is cleaner and seems to
143 // work with EV5 PAL code, but not the other way around.
144 if (!tc->misspeculating()
145 && !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) {
146 // set VA register with faulting address
147 tc->setMiscRegNoEffect(AlphaISA::IPR_VA, vaddr);
147 tc->setMiscRegNoEffect(IPR_VA, vaddr);
148
149 // set MM_STAT register flags
148
149 // set MM_STAT register flags
150 tc->setMiscRegNoEffect(AlphaISA::IPR_MM_STAT,
151 (((AlphaISA::Opcode(tc->getInst()) & 0x3f) << 11)
152 | ((AlphaISA::Ra(tc->getInst()) & 0x1f) << 6)
150 tc->setMiscRegNoEffect(IPR_MM_STAT,
151 (((Opcode(tc->getInst()) & 0x3f) << 11)
152 | ((Ra(tc->getInst()) & 0x1f) << 6)
153 | (flags & 0x3f)));
154
155 // set VA_FORM register with faulting formatted address
153 | (flags & 0x3f)));
154
155 // set VA_FORM register with faulting formatted address
156 tc->setMiscRegNoEffect(AlphaISA::IPR_VA_FORM,
157 tc->readMiscRegNoEffect(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
156 tc->setMiscRegNoEffect(IPR_VA_FORM,
157 tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
158 }
159
160 AlphaFault::invoke(tc);
161}
162
163void ItbFault::invoke(ThreadContext * tc)
164{
165 if (!tc->misspeculating()) {
158 }
159
160 AlphaFault::invoke(tc);
161}
162
163void ItbFault::invoke(ThreadContext * tc)
164{
165 if (!tc->misspeculating()) {
166 tc->setMiscRegNoEffect(AlphaISA::IPR_ITB_TAG, pc);
167 tc->setMiscRegNoEffect(AlphaISA::IPR_IFAULT_VA_FORM,
168 tc->readMiscRegNoEffect(AlphaISA::IPR_IVPTBR) |
169 (AlphaISA::VAddr(pc).vpn() << 3));
166 tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
167 tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
168 tc->readMiscRegNoEffect(IPR_IVPTBR) |
169 (VAddr(pc).vpn() << 3));
170 }
171
172 AlphaFault::invoke(tc);
173}
174
175#else
176
177void ItbPageFault::invoke(ThreadContext * tc)

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171
172 AlphaFault::invoke(tc);
173}
174
175#else
176
177void ItbPageFault::invoke(ThreadContext * tc)

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