faults.cc (5004:7d94cedab264) faults.cc (5184:8782de2949e5)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 163 unchanged lines hidden (view full) ---

172 AlphaFault::invoke(tc);
173}
174
175#else
176
177void ItbPageFault::invoke(ThreadContext * tc)
178{
179 Process *p = tc->getProcessPtr();
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 163 unchanged lines hidden (view full) ---

172 AlphaFault::invoke(tc);
173}
174
175#else
176
177void ItbPageFault::invoke(ThreadContext * tc)
178{
179 Process *p = tc->getProcessPtr();
180 Addr physaddr;
181 bool success = p->pTable->translate(pc, physaddr);
180 TlbEntry entry;
181 bool success = p->pTable->lookup(pc, entry);
182 if(!success) {
183 panic("Tried to execute unmapped address %#x.\n", pc);
184 } else {
185 VAddr vaddr(pc);
182 if(!success) {
183 panic("Tried to execute unmapped address %#x.\n", pc);
184 } else {
185 VAddr vaddr(pc);
186 VAddr paddr(physaddr);
187
188 TlbEntry entry;
189 entry.tag = vaddr.vpn();
190 entry.ppn = paddr.vpn();
191 entry.xre = 15; //This can be read in all modes.
192 entry.xwe = 1; //This can be written only in kernel mode.
193 entry.asn = p->M5_pid; //Address space number.
194 entry.asma = false; //Only match on this ASN.
195 entry.fonr = false; //Don't fault on read.
196 entry.fonw = false; //Don't fault on write.
197 entry.valid = true; //This entry is valid.
198
199 tc->getITBPtr()->insert(vaddr.page(), entry);
200 }
201}
202
203void NDtbMissFault::invoke(ThreadContext * tc)
204{
205 Process *p = tc->getProcessPtr();
186 tc->getITBPtr()->insert(vaddr.page(), entry);
187 }
188}
189
190void NDtbMissFault::invoke(ThreadContext * tc)
191{
192 Process *p = tc->getProcessPtr();
206 Addr physaddr;
207 bool success = p->pTable->translate(vaddr, physaddr);
193 TlbEntry entry;
194 bool success = p->pTable->lookup(vaddr, entry);
208 if(!success) {
209 p->checkAndAllocNextPage(vaddr);
195 if(!success) {
196 p->checkAndAllocNextPage(vaddr);
210 success = p->pTable->translate(vaddr, physaddr);
197 success = p->pTable->lookup(vaddr, entry);
211 }
212 if(!success) {
213 panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
214 } else {
198 }
199 if(!success) {
200 panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
201 } else {
215 VAddr paddr(physaddr);
216
217 TlbEntry entry;
218 entry.tag = vaddr.vpn();
219 entry.ppn = paddr.vpn();
220 entry.xre = 15; //This can be read in all modes.
221 entry.xwe = 15; //This can be written in all modes.
222 entry.asn = p->M5_pid; //Address space number.
223 entry.asma = false; //Only match on this ASN.
224 entry.fonr = false; //Don't fault on read.
225 entry.fonw = false; //Don't fault on write.
226 entry.valid = true; //This entry is valid.
227
228 tc->getDTBPtr()->insert(vaddr.page(), entry);
229 }
230}
231
232#endif
233
234} // namespace AlphaISA
235
202 tc->getDTBPtr()->insert(vaddr.page(), entry);
203 }
204}
205
206#endif
207
208} // namespace AlphaISA
209